Memory cell array circuit and method of forming the same

ABSTRACT

A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a divisional of U.S. application Ser. No. 16/401,486, filed May 2, 2019, now U.S. Pat. No. 11,151,296, issued Oct. 19, 2021, which claims the benefit of U.S. Provisional Application No. 62/673,786, filed May 18, 2018, which are herein incorporated by reference in their entireties.

BACKGROUND

The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to address issues in a number of different areas. Some of these digital devices, such as memory macros, are configured for the storage of data. As ICs have become smaller and more complex, the resistance of conductive lines within these digital devices are also changed affecting the operating voltages of these digital devices and overall IC performance.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains drawings/photographs executed in color. Copies of this patent with color drawing(s)/photograph(s) will be provided by the Office upon request and payment of the necessary fee.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a circuit diagram of a memory cell, in accordance with some embodiments.

FIG. 2 is a block diagram of a memory cell array having a plurality of memory cells in FIG. 1, in accordance with some embodiments.

FIG. 3 is a schematic diagram of a memory circuit, in accordance with some embodiments.

FIGS. 4A-4H are diagrams of a layout design, in accordance with some embodiments.

FIGS. 5A, 5B, 5C, 5D and 5E are cross-sectional views of a memory circuit, in accordance with some embodiments.

FIG. 6 is a flowchart of a method of forming or manufacturing a memory circuit in accordance with some embodiments.

FIG. 7 is a flowchart of a method of generating a layout design of a memory circuit in accordance with some embodiments.

FIG. 8 is a schematic view of a system for designing an IC layout design in accordance with some embodiments.

FIG. 9 is a block diagram of an IC manufacturing system, and an IC manufacturing flow associated therewith, in accordance with at least one embodiment of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In accordance with some embodiments, a memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line and a source line. The second column of memory cells is separated from the first column of memory cells in a first direction. The first column of memory cells and the second column of memory cells are arranged in a second direction different from the first direction. The first bit line is coupled to the first column of memory cells, and extends in the second direction. The second bit line is coupled to the second column of memory cells, and extends in the second direction. The source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells, and is shared by the first column of memory cells and the second column of memory cells.

In some embodiments, the source line includes a first conductive line extending in the second direction, and being located on a first metal layer. In some embodiments, the source line further includes a second conductive line and a set of vias. In some embodiments, the second conductive line extends in the second direction, and is located on a second metal layer above the first metal layer. In some embodiments, the set of vias electrically couple the first conductive line and the second conductive line.

In some embodiments, a resistance of the first bit line or a resistance of the second bit line is substantially equal to a resistance of the source line.

In some embodiments, the first or second bit line includes a third conductive line extending in the second direction, and being located on a third metal layer. In some embodiments, the first or second bit line further includes a fourth conductive line and another set of vias. In some embodiments, the fourth conductive line extends in the second direction, and is located on a fourth metal layer above the third metal layer. In some embodiments, the another set of vias electrically couple the third conductive line and the fourth conductive line.

In some embodiments, memory cell array includes source lines SL shared by adjacent columns of memory cells causing a decrease in the number of source lines and corresponding routing tracks than other approaches. In some embodiments, by having less source lines and corresponding routing tracks, the width of source lines and corresponding routing tracks in the memory cell array is increased resulting in less source line resistance than other approaches. In some embodiments, by having less source line resistance, a difference between the source line resistance and bit line resistance is smaller than other approaches. In some embodiments, by having a smaller difference between source line resistance and bit line resistance than other approaches results in simpler peripheral circuitry for reading and writing to memory cell array.

Memory Cell

FIG. 1 is a circuit diagram of a memory cell 100, in accordance with some embodiments.

Memory cell 100 is a resistive random access memory (RRAM) cell used for illustration. Other types of memory are within the scope of various embodiments. For example, in some embodiments, memory cell 102 includes a ferroelectric RAM (F-RAM), a Magnetoresistive RAM (MRAM), Phase-change memory (PCM), other forms of non-volatile RAM cells, or the like. Memory cell 100 is configured to store a logic “1” or a logic “0” based on the resistance the memory cell.

Memory cell 100 comprises a selector element (SE) 102 and a resistive switching element (RE) 104. In some embodiments, memory cell 100 is referred to as a “1T1R” (one transistor, one resistor) architecture. In some embodiments, memory cell 100 employs a number of transistors or resistive elements other than one.

Selector element 102 is an N-type metal oxide semiconductor (NMOS) transistor N1. In some embodiments, selector element 102 is a P-type metal oxide semiconductor (PMOS) transistor. Other types of transistors or numbers of transistors in selector element 102 are within the contemplated scope of the present disclosure. In some embodiments, selector element 102 includes one or more diode elements or diode coupled transistors. In some embodiments, selector element 102 includes one or more elements capable of exhibiting switching behavior or function.

A gate terminal of NMOS transistor N1 is coupled to a word line WL1, and is configured to receive a word line signal (not labelled). A drain terminal of NMOS transistor N1 is coupled with resistive switching element 104. A source terminal of NMOS transistor N1 is coupled to a source line SL1, and is configured to output/receive a source line signal (not labelled) to/from the source line SL1. In some embodiments, the source terminal of NMOS transistor N1 is coupled to resistive switching element 104, and the drain terminal of NMOS transistor N1 is coupled to the source line SL1.

Resistive switching element 104 includes a bottom electrode 104 a, a resistive switching material 104 b, and a top electrode 104 c. Resistive switching element 104 is configured to store a logic “F” or a logic “0” based on a variable resistance of the resistive switching material 104 b. In some embodiments, the resistance of the resistive switching material 104 b is adjusted based on at least a voltage applied to the word line WL1, bit line BL1 or source line SL1.

Bottom electrode (BE) 104 a is coupled to the drain of NMOS transistor N1. Top electrode (TE) 104 c is coupled to the bit line BL1. BE 104 a and TE 104 c are conductive structures. In some embodiments, a conductive structure includes a metal, a metal compound or a doped semiconductor. In some embodiments, a metal includes at least Cu (Copper), Co, W, Ru, Al, or the like. In some embodiments, a metal compound includes at least AlCu, W—TiN, TiSix, NiSix, TiN, TaN, or the like. In some embodiments, a doped semiconductor includes at least doped silicon, or the like.

Resistive switching material 104 b is positioned between BE 104 and TE 104 c. In some embodiments, resistive switching material 104 b is a dielectric material having one or more layers. In some embodiments, dielectric materials include one or more transition metal oxides (TMO). In some embodiments, TMOs include at least one selected from the group consisting of HfOx, TaOx, TiOx, AlOx, CuOx, NiOx, WOx, mixtures thereof, and alloys thereof. In some embodiments, dielectric materials include one or more binary oxides. In some embodiments, binary oxides include at least one selected from the group consisting of VOx, CrOx, MnOx, FeOx, CoOx, ZnOx, YOx, ZrOx, NbOx, MoOx, RuOx, AgOx, SiOx, CeOx, mixtures thereof, and alloys thereof. In some embodiments, dielectric materials include one or more ternary oxides. In some embodiments, ternary oxides include at least one selected from the group consisting of SrZrOx, SrTiOx, mixtures thereof, and alloys thereof. In some embodiments, dielectric materials include one or more quaternary oxides. In some embodiments, quaternary oxides include at least one selected from the group consisting of Cd_(m)Ce_(n)Fe_(x)O_(y), mixtures thereof, and alloys thereof.

In some embodiments, the resistive switching material 104 b is changed from a low resistance state, known as a “Set,” to a high resistance state, known as a “Reset,” and vice versa.

In some embodiments, the resistive switching material 104 b is “Set” by applying at least a voltage to a corresponding word line WL1, bit line BL1 or source line SL1 such that a filament or conduction path through the resistive switching material 104 b is formed or re-formed.

In some embodiments, the resistive switching material 104 b is “Reset” by applying at least a voltage to a corresponding word line WL1, bit line BL1 or source line SL1 such that the filament or conduction path through the resistive switching material 104 b is broken.

Memory Cell Array

FIG. 2 is a block diagram of a memory cell array 200 having a plurality of memory cells in FIG. 1, in accordance with some embodiments. For example, memory cell 100 of FIG. 1 is usable as one or more memory cells in memory cell array 200.

Memory cell array 200 comprises an array of memory cells 202[1,1], 202[1,2], . . . , 202[2,2], . . . , 202[M,N] (collectively referred to as “array of memory cells 202A”) having M rows and N columns, where N is a positive integer corresponding to the number of columns in array of memory cells 202A and M is a positive integer corresponding to the number of rows in array of memory cells 202A. The rows of cells in array of memory cells 202A are arranged in a first direction X. The columns of cells in array of memory cells 202A are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. Memory cell 100 of FIG. 1 is usable as one or more memory cells in array of memory cells 202A.

Each memory cell 202[1,1], 202[1,2], . . . , 202[2,2], . . . , 202[M,N] in array of memory cells 202A includes a corresponding resistive switching element RE1 coupled to a corresponding selector element SE1. Resistive switching element 104 of FIG. 1 is usable as one or more resistive switching elements RE1 in memory cell array 200, and similar detailed description is therefore omitted. Selector element 102 of FIG. 1 is usable as one or more selector elements SE1 in memory cell array 200, and similar detailed description is therefore omitted.

Different types of memory cells in memory cell array 200 are within the contemplated scope of the present disclosure. Different configurations of array of memory cells 202A are within the contemplated scope of the present disclosure. Different configurations of bit lines BL, word lines WL or source lines SL in array of memory cells 202A are within the contemplated scope of the present disclosure. Furthermore, in some embodiments, array of memory cells 202A includes multiple groups of different types of memory cell.

Memory cell array 200 further includes M word lines WL[1], . . . WL[M] (collectively referred to as “word line WL”). Each row 1, . . . , M in array of memory cells 202A is associated with a corresponding word line WL[1], . . . , WL[M]. Each word line WL extends in the first direction X. One or more of the word lines of the set of word lines WL in array of memory cells 202A corresponds to the word line WL1 of FIG. 1.

Memory cell array 200 further includes N bit lines BL[1], . . . BL[N] (collectively referred to as “bit line BL”). Each column 1, . . . , N in array of memory cells 202A is associated with a corresponding bit line BL[1], . . . , BL[N]. Each bit line BL extends in the second direction Y. One or more bit lines of the set of bit lines BL in array of memory cells 202A corresponds to bit line BL1 of FIG. 1.

Memory cell array 200 further includes X source lines SL[1], . . . SL[X] (collectively referred to as “source line SL”), where X is a positive integer corresponding to the number of source lines. In some embodiments, for an even number of columns N in array of memory cells 202A, integer X is equal to N/2. In some embodiments, for an odd number of columns N in array of memory cells 202A, integer X is equal to (N+1)/2.

In some embodiments, each source line SL[1], . . . , SL[X] is positioned between a corresponding pair of bit lines BL[1], . . . , BL[N]. In some embodiments, adjacent columns of memory cells in array of cells 202A are configured to share a single source line of the set of source lines SL. For example, source line SL1 is shared by columns 1 and 2 of array of cells 202A. Similarly, source line SL2 is shared by columns 2 and 3 of array of cells 202A. Similarly, source line SLX is shared by columns N−1 and N of array of cells 202A.

Each source line SL extends in the second direction Y. One or more source lines of the set of source lines SL in array of memory cells 202A corresponds to source line SL1 of FIG. 1.

In some embodiments, a memory cell of array of memory cells 202A is positioned between an adjacent bit line of bit lines BL and an adjacent source line of source lines SL. For example, in row 1 and column 1 of memory cell array 200, memory cell 202[1,1] is positioned between bit line BL[1] and source line SL[1]. Similarly, in row 1 and column 2 of memory cell array 200, memory cell 202[1,2] is positioned between source line SL[1] and bit line BL[2].

Each resistive switching element RE1 is coupled between a corresponding bit line of bit lines BL and a corresponding drain terminal of a corresponding selector element SE1. Each gate terminal of a corresponding selector element SE1 is coupled to a corresponding word line of word lines WL. Source terminals of a pair of adjacent selector element SE1 are coupled to a corresponding source line of source lines SL. In other words, source lines SL are shared amongst adjacent columns of memory cells in memory cell array 200.

For example, resistive switching element RE1 of memory cell 202[1,1] is coupled to bit line BL[1], the gate terminal of selector element SE1 of memory cell 202[1,1] is coupled to word line WL[1], and the source terminal of selector element SE1 of memory cell 202[1,1] is coupled to source line SL1. Similarly, resistive switching element RE1 of memory cell 202[1,2] is coupled to bit line BL[2], the gate terminal of selector element SE1 of memory cell 202[1,2] is coupled to word line WL[1], and the source terminal of selector element SE1 of memory cell 202[1,2] is coupled to source line SL1. Source line SL1 is shared by selector element SE1 of memory cell 202[1,1] and selector element SE1 of memory cell 202[1,1].

In some embodiments, memory cell array 200 includes source lines SL shared by adjacent columns of memory cells causing a decrease in the number of source lines and corresponding routing tracks than other approaches.

In some embodiments, by having less source lines and corresponding routing tracks, the width of source lines and corresponding routing tracks in memory cell array 200 is increased resulting in less source line resistance than other approaches.

In some embodiments, by having less source line resistance, a difference between the source line resistance and bit line resistance is smaller than other approaches. In some embodiments, by having a smaller difference between source line resistance and bit line resistance than other approaches results in simpler peripheral circuitry for reading and writing to memory cell array 200.

In some embodiments, by memory cell array 200 or memory circuit 300 (FIG. 3) or memory circuit 500 (FIGS. 5A-5E) having less source lines and corresponding routing tracks, memory cell array 200, memory circuit 300 or memory circuit 500 occupies less area than other memory cell arrays or memory circuits. In some embodiments, by occupying less area than other memory cell arrays, memory cell array 200, memory circuit 300 or memory circuit 500 is denser and has a larger memory capacity compared with other approaches.

Memory Circuit

FIG. 3 is a schematic diagram of a memory circuit 300, in accordance with some embodiments. Memory circuit 300 is an embodiment of the block diagram of memory cell array 200 of FIG. 2 expressed in a schematic diagram.

Memory circuit 300 relates to memory cell array 200 of FIG. 2. Memory circuit 300 includes a memory cell array 302. Memory circuit 300 is a schematic representation of two adjacent columns and two adjacent rows of a memory cell array 302. Memory cell array 302 is similar to memory cell array 200 of FIG. 2, and similar detailed description is therefore omitted.

Memory cell array 302 includes memory cells 302[1,1], 302[1,2], 302[2,1], and 302[2,2], bit lines BL1 and BL2, word lines WL1 and WL2, and a source line SL1.

Memory cells 302[1,1], 302[1,2], 302[2,1], and 302[2,2] are similar to corresponding memory cells 202[1,1], 202[1,2], 202[2,1], and 202[2,2] of FIG. 2, and similar detailed description is therefore omitted. Bit lines BL1 and BL2 are similar to corresponding bit lines BL[1] and BL[2] of FIG. 2, and similar detailed description is therefore omitted. Word lines WL1 and WL2 are similar to corresponding word lines WL[1] and WL[2] of FIG. 2, and similar detailed description is therefore omitted. Source line SL1 is similar to source line SL[1] of FIG. 2, and similar detailed description is therefore omitted.

Memory cells 302[1,1], 302[1,2], 302[2,1], and 302[2,2] include corresponding selector elements 314 a, 314 b, 314 c and 314 d coupled to corresponding resistive switching elements 350 a, 350 b, 350 c and 350 d. Selector elements 314 a, 314 b, 314 c, and 314 d are similar to selector elements SE1 of FIG. 2, and similar detailed description is therefore omitted. Resistive switching elements 350 a, 350 b, 350 c, and 350 d are similar to resistive switching elements RE1 of FIG. 2, and similar detailed description is therefore omitted.

Selector element 314 a is a transistor device with an active region 310 and 2 gate portions 316 a and 316 b (e.g., fingers) of word line WL1. In some embodiments, active region 310 of selector element 314 a or 314 c or active region 312 (described below) of selector element 314 b or 314 d is referred to as an oxide definition (OD) region which defines the source or drain diffusion regions of memory device 300. A source of active region 310 of selector element 314 a is coupled to the source line SL1. A drain of active region 310 of selector element 314 a is coupled to resistive switching element 350 a by a conductive structure 320 a and a conductive structure 330 a. Resistive switching element 350 a is positioned between conductive structure 320 a and conductive structure 340 a. Resistive switching element 350 a is coupled to bit line BL1 by the conductive structure 340 a.

Selector element 314 b is a transistor device with an active region 310 and 2 gate portions 318 a and 318 b (e.g., fingers) of word line WL2. A source of active region 310 of selector element 314 b is coupled to the source line SL1. A drain of active region 310 of selector element 314 b is coupled to resistive switching element 350 b by a conductive structure 320 b and a conductive structure 330 b. Resistive switching element 350 b is positioned between conductive structure 320 b and conductive structure 340 b. Resistive switching element 350 b is coupled to bit line BL1 by the conductive structure 340 b.

Selector element 314 c is a transistor device with an active region 312 and 2 gate portions 316 a and 316 b (e.g., fingers) of word line WL1. A source of active region 312 of selector element 314 c is coupled to the source line SL1. A drain of active region 312 of selector element 314 c is coupled to resistive switching element 350 c by a conductive structure 320 c and a conductive structure 330 c. Resistive switching element 350 c is positioned between conductive structure 320 c and conductive structure 340 c. Resistive switching element 350 c is coupled to bit line BL2 by the conductive structure 340 b.

Selector element 314 d is a transistor device with an active region 312 and 2 gate portions 318 a and 318 b (e.g., fingers) of word line WL2. A source of active region 312 of selector element 314 d is coupled to the source line SL1. A drain of active region 312 of selector element 314 d is coupled to resistive switching element 350 d by a conductive structure 320 d and a conductive structure 330 b. Resistive switching element 350 d is positioned between conductive structure 320 d and conductive structure 340 d. Resistive switching element 350 d is coupled to bit line BL2 by the conductive structure 340 d.

In some embodiments, at least word line WL1 or WL2 is in a polysilicon (POLY) layer of memory circuit 300.

The source line SL1 is coupled to the source of active region 310 of selector elements 314 a and 314 b and the source of active region 312 of selector elements 314 c and 314 d. In some embodiments, source line SL1 is in a metal one (M1) layer of memory circuit 300. In some embodiments, source line SL1 is in the M1 layer and a metal two (M2) layer of memory circuit 300. In some embodiments, at least conductive structure 330 a, 330 b, 330 c or 330 d is in the M1 layer of memory circuit 300. In some embodiments, at least conductive structure 330 a, 330 b, 330 c or 330 d is in the M1 and M2 layer of memory circuit 300.

In some embodiments, at least conductive structure 320 a, 320 b, 320 c or 320 d is in in a metal three (M3) layer of memory circuit 300.

In some embodiments, at least conductive structure 340 a, 340 b, 340 c or 340 d is in a metal four (M4) layer of memory circuit 300. In some embodiments, at least resistive switching element 350 a, 350 b, 350 c or 350 d is between the M3 and the M4 layer of memory circuit 300.

In some embodiments, at least bit line BL1 or BL2 is in the M4 layer of memory circuit 300. In some embodiments, at least bit line BL1 or BL2 is in the M4 layer and a metal five (M5) layer of memory circuit 300.

In some embodiments, the POLY layer is below the M1 layer. In some embodiments, the M1 layer is below the M2 layer. In some embodiments, the M2 layer is below the M3 layer. In some embodiments, the M3 layer is below the M4 layer. In some embodiments, the M4 layer is below the M5 layer. Other metal layers are within the scope of the present disclosure.

In some embodiments, memory circuit 300 also includes other circuits (e.g., other driver circuits, timing circuits, decoder circuits, etc.) that are not described for simplicity.

Layout Design of Memory Circuit

FIGS. 4A-4H are diagrams of a layout design 400, in accordance with some embodiments. Layout design 400 is a layout diagram of memory circuit 300 of FIG. 3 or memory cell 100 of FIG. 1. Layout design 400 is usable to manufacture memory cell 100, memory circuit 300 or 500.

FIG. 4A is a diagram of layout design 400. For ease of illustration, some of the labeled elements of FIGS. 4B-4H are not labelled in FIG. 4A. In some embodiments, FIGS. 4A-4H include additional elements not shown in FIGS. 4A-4H.

FIGS. 4B-4H are diagrams of a corresponding portion 400B-400H of layout design 400 of FIG. 4A, simplified for ease of illustration. Portion 400B includes one or more features of layout design 400 of FIG. 4A from the active (OD) level to the metal one (M1) level of layout design 400. Portion 400C includes one or more features of layout design 400 of FIG. 4A from the M1 level to the M2 level of layout design 400. Portion 400D includes one or more features of layout design 400 of FIG. 4A from the M2 level to the M3 level of layout design 400. Portion 400E includes one or more features of layout design 400 of FIG. 4A from the M3 level to the TE level of layout design 400. Portion 400F includes one or more features of layout design 400 of FIG. 4A from the M3 level to the M4 level of layout design 400. Portion 400G includes one or more features of layout design 400 of FIG. 4A from the M4 level and via four (V4) level of layout design 400. Portion 400H includes one or more features of layout design 400 of FIG. 4A from the M5 level and V4 level of layout design 400.

Layout design 400 includes one or more of memory cell layout patterns 402[1,1], 402[1,2], 402[2,1] or 402[2,2]. Memory cell layout patterns 402[1,1], 402[1,2], 402[2,1] and 402[2,2] are useable to manufacture corresponding memory cells 302[1,1], 302[1,2], 302[2,1] and 302[2,2] of memory circuit 300 of FIG. 3.

In some embodiments, memory cell layout pattern 402[1,1], 402[1,2], 402[2,1], 402[2,2] include at least a corresponding selector element layout pattern 404 a, 404 b, 404 c, 404 d and a corresponding resistive switching element layout pattern 450 a, 450 b, 450 c, 450 d (described below.)

In some embodiments, selector element layout pattern 404 a includes at least metal over diffusion layout patterns 420 a, 422 a, 422 b, gate layout patterns 416 a, 416 b or active region layout pattern 410 (described below.)

In some embodiments, selector element layout pattern 404 b includes at least metal over diffusion layout patterns 420 b, 422 b, 422 c, gate layout patterns 418 a, 418 b or active region layout pattern 410 (described below.)

In some embodiments, selector element layout pattern 404 c includes at least metal over diffusion layout patterns 420 c, 422 d, 422 e, gate layout patterns 416 a, 416 b or active region layout pattern 412 (described below.)

In some embodiments, selector element layout pattern 404 d includes at least metal over diffusion layout patterns 420 d, 422 e, 422 f, gate layout patterns 418 a, 418 b or active region layout pattern 412 (described below.)

Layout design 400 includes active region layout patterns 410, 412 (collectively referred to as a “set of active region layout patterns 411”) extending in the second direction Y. Active region layout patterns 410, 412 of the set of active region layout patterns 411 are separated from one another in the first direction X. Active region layout patterns 410, 412 are usable to manufacture corresponding active regions 310, 312 of FIG. 3 or corresponding active regions 510, 512 (FIGS. 4A-4E) of memory circuit 500. In some embodiments, the set of active region layout patterns 411 is located on a first layout level. Other configurations or quantities of patterns in the set of active region layout patterns 411 are within the scope of the present disclosure.

Active region layout pattern 410 is part of memory cell layout patterns 402[1,1] and 402[1,2].

Layout design 400 further includes gate layout patterns 416 a, 416 b, 418 a, 418 b (collectively referred to as a “set of gate layout patterns 416”) each extending in the first direction X. Each of the layout patterns of the set of gate layout patterns 416 is separated from an adjacent layout pattern of the set of gate layout patterns 416 in the second direction Y by a first pitch.

Gate layout patterns 416 a, 416 b, 418 a, 418 b are usable to manufacture corresponding gates 316 a, 316 b, 318 a, 318 b of FIG. 3. Gate layout patterns 416 a, 416 b are usable to manufacture corresponding gates 516 a, 516 b (FIGS. A-5E) of memory circuit 500. The set of gate layout patterns 416 are positioned on a second layout level (POLY) different from the first layout level. The set of active region layout patterns 411 is below the set of gate layout patterns 416.

Gate layout pattern 416 a, 416 b, 416 c, 416 d is usable to manufacture the gate terminal of NMOS transistor N1 of corresponding selector element 314 a, 314 b, 314 c, 314 d of FIG. 3. Other configurations or quantities of patterns in the set of gate layout patterns 416 are within the scope of the present disclosure.

Layout design 400 further includes metal over diffusion layout patterns 420 a, 420 b, 420 c, 420 d (hereinafter referred to as a “set of metal over diffusion layout patterns 420”) and metal over diffusion layout patterns 422 a, 422 b, 422 c, 422 d, 422 e, 422 f (hereinafter referred to as a “set of metal over diffusion layout patterns 422”). In some embodiments, the set of metal over diffusion layout patterns 420 or 422 extends in at least the first direction X or the second direction Y.

Each of the layout patterns of the set of metal over diffusion layout patterns 420 or 422 is separated from an adjacent layout pattern of the set of metal over diffusion layout patterns 210 in at least the first direction X or the second direction Y. The set of metal over diffusion layout patterns is located on a third layout level. In some embodiments, the third layout level of layout design 400 is a metal over diffusion (MD) level. In some embodiments, the MD level is positioned above at least the active region of layout design 400.

In some embodiments, the set of metal over diffusion layout patterns 420 or 422 includes one or more features of layout patterns located on a via over diffusion (VD) level, a metal zero (M0) level or a via zero (V0) level of layout design 400 that is not shown for brevity. For example, in some embodiments, the third layout level may also include the M0 level, the POLY level or the MD level of layout design 400. In some embodiments, the set of metal over diffusion layout patterns 420 or 422 further includes via layout patterns useable to manufacture a corresponding set of vias that are coupled to upper metal layers (e.g., conductive feature layout patterns 414 a, 414 b, 414 c, 414 d, 414 e).

The set of metal over diffusion layout patterns 420 or 422 is usable to manufacture a corresponding set of contacts 520 or 522 (FIGS. 5A-5E) of memory circuit 500.

In some embodiments, metal over diffusion layout pattern 420 a is usable to manufacture at least a drain terminal of NMOS transistor N1 of memory cell 202[1,1] of FIG. 2 or memory cell 302[1,1] of FIG. 3. In some embodiments, metal over diffusion layout pattern 420 b is usable to manufacture at least a drain terminal of NMOS transistor N1 of memory cell 202[2,1] of FIG. 2 or memory cell 302[2,1] of FIG. 3. In some embodiments, metal over diffusion layout pattern 420 c is usable to manufacture at least a drain terminal of NMOS transistor N1 of memory cell 202[1,2] of FIG. 2 or memory cell 302[1,2] of FIG. 3. In some embodiments, metal over diffusion layout pattern 420 d is usable to manufacture at least a drain terminal of NMOS transistor N1 of memory cell 202[2,2] of FIG. 2 or memory cell 302[2,2] of FIG. 3.

In some embodiments, metal over diffusion layout pattern 422 a or 422 b is usable to manufacture at least a source terminal of NMOS transistor N1 of memory cell 202[1,1] of FIG. 2 or memory cell 302[1,1] of FIG. 3. In some embodiments, metal over diffusion layout pattern 422 b or 422 c is usable to manufacture at least a source terminal of NMOS transistor N1 of memory cell 202[2,1] of FIG. 2 or memory cell 302[2,1] of FIG. 3. In some embodiments, metal over diffusion layout pattern 422 d or 422 e is usable to manufacture at least a source terminal of NMOS transistor N1 of memory cell 202[1,2] of FIG. 2 or memory cell 302[1,2] of FIG. 3. In some embodiments, metal over diffusion layout pattern 422 e or 422 f is usable to manufacture at least a source terminal of NMOS transistor N1 of memory cell 202[2,2] of FIG. 2 or memory cell 302[2,2] of FIG. 3.

Metal over diffusion layout patterns 420 a, 420 b, 422 a, 422 b, 422 c are above active region layout pattern 410. Metal over diffusion layout patterns 420 c, 420 d, 422 d, 422 e, 422 f are above active region layout pattern 412. Other configurations or quantities of patterns in the set of metal over diffusion layout patterns 420 or 422 are within the scope of the present disclosure.

Layout design 400 further includes conductive feature layout patterns 414 a, 414 b, 414 c, 414 d, 414 e (hereinafter referred to as a “set of conductive feature layout patterns 414”) extending in the second direction Y. In some embodiments, the set of conductive feature layout patterns 414 extends in two directions (e.g., first direction X or second direction Y). The set of conductive feature layout patterns 414 includes one or more conductive feature layout patterns. The set of conductive feature layout patterns 414 is located on a fourth layout level. In some embodiments, the fourth layout level of layout design 400 is metal one (M1). In some embodiments, the M1 level is positioned above at least the active region, the M0 level, the POLY level or the MD level of layout design 400.

The set of conductive feature layout patterns 414 is usable to manufacture a corresponding set of conductive structures 514 (FIGS. 5A-5E) of memory circuit 500. Conductive feature layout patterns 414 a, 414 b, 414 c, 414 d are usable to manufacture corresponding conductive structures 330 a, 330 b, 330 c, 330 d of FIG. 3. Conductive feature layout pattern 414 e is usable to manufacture source line SL1 FIG. 3 or conductive structure 514 e (FIGS. 5A-5E) of memory circuit 500.

Conductive feature layout patterns 414 a, 414 c overlap gate layout patterns 416 a, 416 b. Conductive feature layout patterns 414 b, 414 d overlap gate layout patterns 418 a, 418 b. Conductive feature layout pattern 414 e overlaps gate layout patterns 416 a, 416 b, 418 a, 418 b and active region layout patterns 410, 412.

Conductive feature layout patterns 414 a, 414 c overlap corresponding metal over diffusion layout patterns 420 a, 420 c. Conductive feature layout patterns 414 b, 414 d overlap corresponding metal over diffusion layout patterns 420 b, 420 d. Conductive feature layout pattern 414 e overlaps metal over diffusion layout patterns 422 a, 422 b, 422 c, 422 d, 422 e, 422 f.

Conductive feature layout patterns 414 a, 414 b are located above an edge of active region layout pattern 410 associated with corresponding drain regions of NMOS transistor N1 of corresponding selector element 314 a, 314 b of FIG. 3. Conductive feature layout patterns 414 c, 414 d are located above an edge of active region layout pattern 412 associated with corresponding drain regions of NMOS transistor N1 of corresponding selector element 314 c, 314 d of FIG. 3. Conductive feature layout pattern 414 e is located above an edge of active region layout patterns 410 and 412 associated with source regions of NMOS transistor N1 of corresponding selector element 314 a, 314 b, 314 c, 314 d of FIG. 3.

Other configurations or quantities of patterns in the set of conductive feature layout patterns 414 are within the scope of the present disclosure.

Layout design 400 further includes conductive feature layout patterns 424 a, 424 b, 424 c, 424 d, 424 e (hereinafter referred to as a “set of conductive feature layout patterns 424”) extending in the second direction Y. In some embodiments, the set of conductive feature layout patterns 424 extends in two directions (e.g., first direction X or second direction Y). The set of conductive feature layout patterns 424 includes one or more conductive feature layout patterns. The set of conductive feature layout patterns 424 is located on a fifth layout level. In some embodiments, the fifth layout level of layout design 400 is metal two (M2). In some embodiments, the M2 level is positioned above at least the active region, the M0 level, the POLY level, the MD level or the M1 level of layout design 400.

The set of conductive feature layout patterns 424 is usable to manufacture a corresponding set of conductive structures 524 (FIGS. 5A-5E) of memory circuit 500. In some embodiments, conductive feature layout patterns 424 a, 424 b, 424 c, 424 d are usable to manufacture corresponding conductive structures 330 a, 330 b, 330 c, 330 d of FIG. 3. Conductive feature layout pattern 424 e is usable to manufacture source line SL1 FIG. 3 or conductive structure 524 e (FIGS. 5A-5E) of memory circuit 500. In some embodiments, source line SL1 of FIG. 3 or memory circuit 500 of FIGS. 5A-5E includes conductive structures 514 e, 524 e located on two different metal levels, and is manufactured by corresponding conductive feature layout patterns 414 e, 424 e.

Conductive feature layout patterns 424 a, 424 b, 424 c, 424 d, 424 e are above corresponding conductive feature layout patterns 414 a, 414 b, 414 c, 414 d, 414 e. In some embodiments, an edge of at least conductive feature layout pattern 424 a, 424 b, 424 c, 424 d or 424 e is aligned in at least the first direction X or the second direction Y with an edge of a corresponding conductive feature layout pattern 414 a, 414 b, 414 c, 414 d or 414 e.

Conductive feature layout patterns 424 a, 424 c overlap gate layout patterns 416 a, 416 b. Conductive feature layout patterns 424 b, 424 d overlap gate layout patterns 418 a, 418 b. Conductive feature layout pattern 424 e overlaps gate layout patterns 416 a, 416 b, 418 a, 418 b and active region layout patterns 410, 412.

Conductive feature layout patterns 424 a, 424 c overlap corresponding metal over diffusion layout patterns 420 a, 420 c. Conductive feature layout patterns 424 b, 424 d overlap corresponding metal over diffusion layout patterns 420 b, 420 d. Conductive feature layout pattern 424 e overlaps metal over diffusion layout patterns 422 a, 422 b, 422 c, 422 d, 422 e, 422 f.

Conductive feature layout patterns 424 a, 424 b are located above an edge of active region layout pattern 410 associated with corresponding drain regions of NMOS transistor N1 of corresponding selector element 314 a, 314 b of FIG. 3. Conductive feature layout patterns 424 c, 424 d are located above an edge of active region layout pattern 412 associated with corresponding drain regions of NMOS transistor N1 of corresponding selector element 314 c, 314 d of FIG. 3. Conductive feature layout pattern 424 e is located above an edge of active region layout patterns 410 and 412 associated with source regions of NMOS transistor N1 of corresponding selector element 314 a, 314 b, 314 c, 314 d of FIG. 3.

Other configurations or quantities of patterns in the set of conductive feature layout patterns 424 are within the scope of the present disclosure.

Layout design 400 further includes via layout patterns 430 a, 430 b, 430 c, 430 d (collectively referred to as a “set of via layout patterns 430”) and via layout patterns 432 a, 432 b, 432 c, 432 d, 432 e, 432 f (collectively referred to as a “set of via layout patterns 432”).

Set of via layout patterns 430 or 432 are between the set of conductive feature layout patterns 424 and the set of conductive feature layout patterns 414.

Via layout patterns 430 a, 430 b, 430 c, 430 d of the set of via layout patterns 430 are between corresponding conductive feature layout patterns 424 a, 424 b, 424 c, 424 d of the set of conductive feature patterns 424 and corresponding conductive feature layout patterns 414 a, 414 b, 414 c, 414 d of the set of conductive feature patterns 414.

Via layout patterns 432 a, 432 b, 432 c, 432 d, 432 e, 432 f of the set of via layout patterns 432 are between conductive feature layout pattern 424 e of the set of conductive feature patterns 424 and conductive feature layout pattern 414 e of the set of conductive feature patterns 414.

The set of via layout patterns 430 and 432 are positioned at a V1 level of layout design 400. In some embodiments, the V1 level is between the M1 level and the M2 level. In some embodiments, the V1 level is positioned above at least the V0 level, the VG level or the VD level of layout design 400.

The set of via layout patterns 430 is usable to manufacture a corresponding set of vias 530 (FIGS. 5A-5E). The set of vias 530 couple at least a member of the set of conductive structures 524 to at least a member of the set of conductive structures 514.

The set of via layout patterns 432 is usable to manufacture a corresponding set of vias 532 (FIGS. 5A-5E). The set of vias 532 couple at least a member of the set of conductive structures 524 to at least a member of the set of conductive structures 514.

In some embodiments, a via layout pattern 430 a, 430 b, 430 c, 430 d of the set of via layout patterns 430 is located where a corresponding conductive feature layout pattern 424 a, 424 b, 424 c, 424 d of the set of conductive feature layout patterns 424 overlaps a corresponding layout pattern 420 a, 420 b, 420 c, 420 d of the set of metal over diffusion layout patterns 420. In some embodiments, a center of via layout pattern 430 a, 430 b, 430 c, 430 d of the set of via layout patterns 430 is below a center of a corresponding conductive feature layout pattern 424 a, 424 b, 424 c, 424 d of the set of conductive feature layout patterns 424.

In some embodiments, a center of via layout pattern 430 a, 430 b, 430 c, 430 d of the set of via layout patterns 430 is aligned in at least the first direction X or the second direction Y with a center of a corresponding layout pattern 420 a, 420 b, 420 c, 420 d of the set of metal over diffusion layout patterns 420 resulting in a source line, manufactured by layout design 400, with a lower source line resistance than other approaches.

In some embodiments, a via layout pattern 432 a, 432 b, 432 c, 432 d, 432 e, 432 f of the set of via layout patterns 432 is located where conductive feature layout pattern 424 e of the set of conductive feature layout patterns 424 overlaps a corresponding layout pattern 422 a, 422 b, 422 c, 422 d, 422 e, 422 f of the set of metal over diffusion layout patterns 422. In some embodiments, a center of via layout pattern 432 a, 432 b, 432 c, 432 d, 432 e, 432 f of the set of via layout patterns 432 is aligned in at least the first direction X or the second direction Y with a center of a corresponding layout pattern 422 a, 422 b, 422 c, 422 d, 422 e, 422 f of the set of metal over diffusion layout patterns 422 resulting in a source line, manufactured by layout design 400, with a lower source line resistance than other approaches.

Other configurations of set of via layout patterns 430 or 432 are within the scope of the present disclosure.

Layout design 400 further includes conductive feature layout patterns 434 a, 434 b, 434 c, 434 d (hereinafter referred to as a “set of conductive feature layout patterns 434”) and conductive feature layout patterns 436 a, 436 b, 436 c (hereinafter referred to as a “set of conductive feature layout patterns 436”).

The set of conductive feature layout patterns 436 extends in the second direction Y. In some embodiments, the set of conductive feature layout patterns 434 extends in at least the first direction X or the second direction Y. In some embodiments, at least one layout pattern of the set of conductive feature layout patterns 434 has a rectangular shape.

The set of conductive feature layout patterns 434 or 436 includes one or more conductive feature layout patterns. The set of conductive feature layout patterns 434 or 436 is located on a sixth layout level. In some embodiments, the sixth layout level of layout design 400 is metal three (M3). In some embodiments, the M3 level is positioned above at least the active region, the M0 level, the POLY level, the MD level, the M1 level or the M2 level of layout design 400.

The set of conductive feature layout patterns 434 is usable to manufacture a corresponding set of conductive structures 534 (FIGS. 5A-5E) of memory circuit 500. In some embodiments, conductive feature layout patterns 434 a, 434 b, 434 c, 434 d are usable to manufacture corresponding conductive structures 320 a, 320 b, 320 c, 320 d of FIG. 3.

Conductive feature layout patterns 436 a, 436 b are usable to manufacture corresponding conductive structures 536 a, 536 b (FIGS. 5A-5E) of memory circuit 500 configured as corresponding word lines WL1, WL2.

Conductive feature layout patterns 434 a, 434 b, 434 c, 434 d are above corresponding conductive feature layout patterns 424 a, 424 b, 424 c, 424 d. The set of conductive feature layout patterns 434 or 436 overlap at least a portion of one or more of conductive feature layout patterns 424 a, 424 b, 424 c, 424 d or 424 e. Conductive feature layout patterns 436 b is positioned between conductive feature layout patterns 434 a, 434 b, 434 c, 434 d.

Other configurations or quantities of patterns in the set of conductive feature layout patterns 434 or 436 are within the scope of the present disclosure.

Layout design 400 further includes via layout patterns 438 a, 438 b, 438 c, 438 d (collectively referred to as a “set of via layout patterns 438”) between the set of conductive feature layout patterns 424 and the set of conductive feature layout patterns 434.

Via layout patterns 438 a, 438 b, 438 c, 438 d of the set of via layout patterns 438 are between corresponding conductive feature layout patterns 424 a, 424 b, 424 c, 424 d of the set of conductive feature patterns 424 and corresponding conductive feature layout patterns 434 a, 434 b, 434 c, 434 d of the set of conductive feature patterns 434.

The set of via layout patterns 438 are positioned at a V2 level of layout design 400. In some embodiments, the V2 level is between the M2 level and the M3 level. In some embodiments, the V2 level is positioned above at least the V0 level, the VG level, the VD level or the V1 level of layout design 400.

The set of via layout patterns 438 is usable to manufacture a corresponding set of vias 538 (FIGS. 5A-5E). The set of vias 538 couple at least a member of the set of conductive structures 524 to at least a member of the set of conductive structures 534.

In some embodiments, a via layout pattern 438 a, 438 b, 438 c, 438 d of the set of via layout patterns 438 is located where a corresponding conductive feature layout pattern 424 a, 424 b, 424 c, 424 d of the set of conductive feature layout patterns 424 is overlapped by a corresponding layout pattern 434 a, 434 b, 434 c, 434 d of the set of conductive feature layout patterns 434.

In some embodiments, a center of via layout pattern 438 a, 438 b, 438 c, 438 d of the set of via layout patterns 438 is aligned in at least the first direction X or the second direction Y with a center of a corresponding via layout pattern 430 a, 430 b, 430 c, 430 d of the set of via layout patterns 430.

Other configurations of set of via layout patterns 438 is within the scope of the present disclosure.

Layout design 400 further includes resistive switching element layout patterns 450 a, 450 b, 450 c, 450 d (hereinafter referred to as a “set of resistive switching element layout patterns 450”.)

The set of resistive switching element layout patterns 450 are usable to manufacture set of resistive switching elements 350 or set of resistive switching elements 550 (FIGS. 5A-5E) of memory circuit 500. In some embodiments, resistive switching element layout patterns 450 a, 450 b, 450 c, 450 d are usable to manufacture corresponding resistive switching elements 350 a, 350 b, 350 c, 350 d of FIG. 3. At least one of the set of resistive switching element layout patterns 450 is usable to manufacture resistive switching element 104 of FIG. 1.

The set of resistive switching element layout patterns 450 is located on a seventh layout level. In some embodiments, the seventh layout level of layout design 400 is above the M3 and below the M4 level. In some embodiments, the seventh layout level is positioned above at least the active region, the M0 level, the POLY level, the MD level, the M1 level, the M2 level or the M3 level of layout design 400.

Resistive switching element layout patterns 450 a, 450 b, 450 c, 450 d include corresponding bottom electrode layout patterns 452 a, 452 b, 452 c, 452 d (hereinafter referred to as a “set of bottom electrode layout patterns 452”), corresponding resistive switching material layout patterns 454 a, 454 b, 454 c, 454 d (hereinafter referred to as a “set of resistive switching material layout patterns 454”) and corresponding top electrode layout patterns 460 a, 460 b, 460 c, 460 d (hereinafter referred to as a “set of top electrode layout patterns 460.”)

The set of bottom electrode layout patterns 452 are usable to manufacture a bottom electrode 104 a of FIG. 1 or a set of bottom electrodes 552 (FIGS. 5A-5E) of memory circuit 500.

The set of bottom electrode layout patterns 452 extends in at least the first direction X or the second direction Y. In some embodiments, at least one layout pattern of the set of bottom electrode layout patterns 452 has a rectangular shape. The set of bottom electrode layout patterns 452 includes one or more bottom electrode layout patterns.

Bottom electrode layout patterns 452 a, 452 b, 452 c, 452 d are above corresponding conductive feature layout patterns 434 a, 434 b, 434 c, 434 d. In some embodiments, a center of bottom electrode layout pattern 452 a, 452 b, 452 c, 452 d of the set of bottom electrode layout patterns 452 is aligned in at least the first direction X or the second direction Y with a center of a corresponding conductive feature layout pattern 434 a, 434 b, 434 c, 434 d of the set of conductive feature layout patterns 434.

The set of resistive switching material layout patterns 454 are usable to manufacture a resistive switching material 104 a of FIG. 1 or a resistive switching material 554 (FIGS. 5A-5E) of memory circuit 500.

The set of resistive switching material layout patterns 454 extends in the second direction Y. In some embodiments, at least one layout pattern of the set of resistive switching material layout patterns 454 has a rectangular shape. The set of resistive switching material layout patterns 454 includes one or more resistive switching material layout patterns.

Resistive switching material layout patterns 454 a, 454 b, 454 c, 454 d overlap at least a portion of corresponding conductive feature layout patterns 434 a, 434 b, 434 c, 434 d. Resistive switching material layout patterns 454 a, 454 b, 454 c, 454 d overlap corresponding bottom electrode layout patterns 452 a, 452 b, 452 c, 452 d. Resistive switching material layout patterns 454 a, 454 b, 454 c, 454 d are above corresponding bottom electrode layout patterns 452 a, 452 b, 452 c, 452 d.

The set of top electrode layout patterns 460 are usable to manufacture a top electrode 104 c of FIG. 1 or a set of top electrodes 560 (FIGS. 5A-5E) of memory circuit 500.

The set of top electrode layout patterns 460 extends in at least the first direction X or the second direction Y. In some embodiments, at least one layout pattern of the set of top electrode layout patterns 460 has a rectangular shape. The set of top electrode layout patterns 460 includes one or more top electrode layout patterns.

Top electrode layout patterns 460 a, 460 b, 460 c, 460 d are above corresponding resistive switching material layout patterns 454 a, 454 b, 454 c, 454 d. In some embodiments, a center of top electrode layout pattern 460 a, 460 b, 460 c, 460 d of the set of top electrode layout patterns 460 is offset in at least the second direction Y with a center of a corresponding bottom electrode layout pattern 452 a, 452 b, 452 c, 452 d of the set of bottom electrode layout patterns 452.

Other configurations or quantities of patterns in the set of resistive switching element layout patterns 450, set of bottom electrode layout patterns 452, set of resistive switching material layout patterns 454, set of top electrode layout patterns 460 are within the scope of the present disclosure.

Layout design 400 further includes conductive feature layout patterns 440 a, 440 b (hereinafter referred to as a “set of conductive feature layout patterns 440”) extending in the second direction Y. The set of conductive feature layout patterns 440 includes one or more conductive feature layout patterns. The set of conductive feature layout patterns 440 is located on an eighth layout level. In some embodiments, the eighth layout level of layout design 400 is metal four (M4). In some embodiments, the M4 level is positioned above at least the active region, the M0 level, the POLY level, the MD level, the M1 level, the M2 level or the M3 level of layout design 400.

The set of conductive feature layout patterns 440 is usable to manufacture set of conductive structures 540 (FIGS. 5A-5E) of memory circuit 500. In some embodiments, conductive feature layout patterns 440 a, 440 b are usable to manufacture corresponding conductive structures 540 a, 540 b (FIGS. 5A-5E) of memory circuit 500. In some embodiments, conductive feature layout pattern 440 a is usable to manufacture conductive structures 340 a, 340 b of FIG. 3. In some embodiments, conductive feature layout pattern 440 b is usable to manufacture conductive structures 340 c, 340 d of FIG. 3. In some embodiments, conductive feature layout patterns 440 a, 440 b are usable to manufacture corresponding bit lines BL1, BL2 of FIG. 3.

Conductive feature layout patterns 440 a, 440 b are above resistive switching element layout patterns 450 a, 450 b, 450 c, 450 d. Conductive feature layout pattern 440 a overlaps resistive switching element layout patterns 450 a, 450 b. Conductive feature layout pattern 440 b overlaps resistive switching element layout patterns 450 c, 450 d. In some embodiments, a center of conductive feature layout patterns 440 a, 440 b is aligned in at least the first direction X with a center of corresponding resistive switching element layout patterns 450 a, 450 b.

Other configurations or quantities of patterns in the set of conductive feature layout patterns 440 are within the scope of the present disclosure.

Layout design 400 further includes conductive feature layout patterns 470 a, 470 b (hereinafter referred to as a “set of conductive feature layout patterns 470”) extending in the second direction Y. The set of conductive feature layout patterns 470 includes one or more conductive feature layout patterns. The set of conductive feature layout patterns 470 is located on a ninth layout level. In some embodiments, the ninth layout level of layout design 400 is metal five (M5). In some embodiments, the M5 level is positioned above at least the active region, the M0 level, the POLY level, the MD level, the M1 level, the M2 level, the M3 or the M4 level of layout design 400.

The set of conductive feature layout patterns 470 is usable to manufacture set of conductive structures 570 (FIGS. 5A-5E) of memory circuit 500. In some embodiments, conductive feature layout patterns 470 a, 470 b are usable to manufacture corresponding conductive structures 570 a, 570 b (FIGS. 5A-5E) of memory circuit 500. In some embodiments, conductive feature layout patterns 470 a, 470 b are usable to manufacture corresponding bit lines BL1, BL2 of FIG. 3 or corresponding conductive structures 570 a, 570 b (FIGS. 5A-5E) of memory circuit 500. In some embodiments, bit line BL1 of FIG. 3 or memory circuit 500 of FIGS. 5A-5E includes conductive structures 540 a, 570 a located on two different metal levels, and is manufactured by corresponding conductive feature layout patterns 440 a, 470 a. In some embodiments, bit line BL2 of FIG. 3 or memory circuit 500 of FIGS. 5A-5E includes conductive structures 540 b, 570 b located on two different metal levels, and is manufactured by corresponding conductive feature layout patterns 440 b, 470 b.

Conductive feature layout patterns 470 a, 470 b are above conductive feature layout patterns 440 a, 440 b. In some embodiments, an edge of at least conductive feature layout pattern 470 a, 470 b is aligned in at least the first direction X or the second direction Y with an edge of a corresponding conductive feature layout pattern 440 a, 440 b. In some embodiments, a center of conductive feature layout patterns 470 a, 470 b is aligned in at least the first direction X or the second direction Y with a center of corresponding conductive feature layout pattern 440 a, 440 b.

Other configurations or quantities of patterns in the set of conductive feature layout patterns 470 are within the scope of the present disclosure.

Layout design 400 further includes via layout patterns 472 a, 472 b, 472 c, 472 d, 472 e, 472 f, 472 g, 472 h (collectively referred to as a “set of via layout patterns 472”) between the set of conductive feature layout patterns 470 and the set of conductive feature layout patterns 440.

Via layout patterns 472 a, 472 b, 472 c, 472 d of the set of via layout patterns 472 are between conductive feature layout pattern 470 a of the set of conductive feature patterns 470 and conductive feature layout pattern 440 a of the set of conductive feature patterns 440.

Via layout patterns 472 e, 472 f, 472 g, 472 h of the set of via layout patterns 472 are between conductive feature layout pattern 470 b of the set of conductive feature patterns 470 and conductive feature layout pattern 440 b of the set of conductive feature patterns 440.

The set of via layout patterns 472 are positioned at a V4 level of layout design 400. In some embodiments, the V4 level is between the M4 level and the M5 level. In some embodiments, the V4 level is positioned above at least the V0 level, the VG level, the VD level, the V1 level or the V2 level of layout design 400.

The set of via layout patterns 472 is usable to manufacture a corresponding set of vias 572 (FIGS. 5A-5E). The set of vias 572 couple at least a member of the set of conductive structures 570 to at least a member of the set of conductive structures 540.

In some embodiments, a center of at least one via layout pattern 472 a, 472 b, 472 c or 472 d of the set of via layout patterns 472 is aligned in at least the first direction X with a center of a layout pattern 450 a or 450 b of the set of resistive switching element layout patterns 450. In some embodiments, a center of at least one via layout pattern 472 e, 472 f, 472 g or 472 h of the set of via layout patterns 472 is aligned in at least the first direction X with a center of a layout pattern 450 c or 450 d of the set of resistive switching element layout patterns 450.

Other configurations of set of via layout patterns 472 is within the scope of the present disclosure.

FIGS. 5A, 5B, 5C, 5D and 5E are cross-sectional views of a memory circuit 500, in accordance with some embodiments. FIG. 5A is a cross-sectional view of a memory circuit 500 corresponding to layout design 400 as intersected by plane A-A′, FIG. 4B is a cross-sectional view of a memory circuit 500 corresponding to layout design 400 as intersected by plane B-B′, FIG. 4C is a cross-sectional view of a memory circuit 500 corresponding to layout design 400 as intersected by plane C-C′, and FIG. 4D is a cross-sectional view of a memory circuit 500 corresponding to layout design 400 as intersected by plane D-D′, in accordance with some embodiments. FIG. 4E is a cross-sectional view of a zoomed in portion of resistive switching element 550 a or 550 c of memory circuit 500, in accordance with some embodiments. Memory circuit 400 is manufactured by layout design 400.

Components that are the same or similar to those in one or more of FIGS. 1-3 and 5A-5E (shown below) are given the same reference numbers, and detailed description thereof is thus omitted.

Memory circuit 500 is manufactured by layout design 400. Structural relationships including alignment, lengths and widths, as well as configurations of memory circuit 500 of FIGS. 5A-5E are similar to the structural relationships and configurations of memory circuit 300 of FIG. 3 or layout design 400 of FIGS. 4A-4H, and will not be described in each of FIGS. 3, 4A-4H and 5A-5E for brevity.

Memory circuit 500 relates to memory circuit 300 of FIG. 3, and similar detailed description is therefore omitted. For example, memory circuit 500 is an implementation of portions of memory cells 302[1,1] and 302[1,2]. In some embodiments, memory circuit 500 is portions of columns 1 and 2 of memory cells 302[1,1] and 302[1,2].

Memory circuit 500 includes memory cells 502 a and 502 b which are similar to memory cells 302[1,1] and 302[1,2] of FIG. 3, and similar detailed description is therefore omitted. In some embodiments, memory cell 502 a includes at least active region 510, contact 520 a, gate 516 a, gate 516 b, contact 522 a or contact 522 b (described below.) In some embodiments, memory cell 502 b includes at least active region 512, contact 520 c, gate 516 a, gate 516 b or contact 522 e (described below.) In some embodiments, memory circuit 500 further includes additional memory cells or features consistent with the descriptions of FIG. 3 or FIGS. 4A-4H.

Memory circuit 500 includes one or more active regions 510, 512 (collectively referred to as “set of active regions 511”) in a substrate (not shown). The set of active regions 511 extends in the second direction Y and is located on a first level of memory circuit 500. Each active region of the set of active regions 511 is separated from each other in the first direction X. In some embodiments, set of active regions 511 of memory circuit 500 is referred to as an oxide definition (OD) region which defines the source or drain diffusion regions of memory circuit 500. In some embodiments, the first level of memory circuit 500 is referred to as the Active/Fin level. In some embodiments, active region 510, 512 includes a set of fins (not shown) extending in the first direction and being below a set of gates 516. In some embodiments, each of the fins (not shown) is separated from an adjacent fin of the set of fins (not shown) by a fin pitch (not shown). Other quantities or configurations of the set of active region 511 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more gates 516 a, 516 b (collectively referred to as “set of gates 516”) extending in the first direction X, overlapping at least the set of active regions 511 and being located on a second level of memory circuit 500. In some embodiments, the second level of memory circuit 500 is different from the first level. In some embodiments, the second level is the POLY level. Each of the gates of the set of gates 516 is separated from an adjacent gate of the set of gates 404 in the second direction Y by a poly pitch. In some embodiments, the second level of memory circuit 500 is referred to as the Poly level.

Gates 516 a, 516 b correspond to the gate terminal of NMOS transistor N1 of selector element 314 a or 314 c of FIG. 3. Other quantities or configurations of the set of gates 516 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more contacts 520 a, 520 c (collectively referred to as a “set of contacts 520”) and contacts 522 a, 522 b, 522 d (collectively referred to as a “set of contacts 522”) extending in at least the first direction X or the second direction Y, overlapping the set of active regions 511, and being located on a third level of memory circuit 500. In some embodiments, the third level of memory circuit 500 is the MD level. In some embodiments, the MD level is positioned above at least the active region of layout design 400. In some embodiments, the set of contacts 520 or 522 further includes vias that are configured to be coupled to upper metal layers (e.g., M1, M2, etc.)

Each of the contacts 520 a, 520 c of the set of contacts 520 is separated from an adjacent contact of the set of contacts 520 in at least the first direction X or the second direction. Each of the contacts 522 a, 522 b, 522 d of the set of contacts 522 is separated from an adjacent contact of the set of contacts 522 in at least the first direction X or the second direction.

In some embodiments, contact 520 a is a drain terminal of NMOS transistor N1 of memory cell 202[1,1] of FIG. 2 or memory cell 302[1,1] of FIG. 3. In some embodiments, contact 520 c is a drain terminal of NMOS transistor N1 of memory cell 202[1,2] of FIG. 2 or memory cell 302[1,2] of FIG. 3.

In some embodiments, contact 522 a or 522 b is at least a source terminal of NMOS transistor N1 of memory cell 202[1,1] of FIG. 2 or memory cell 302[1,1] of FIG. 3. In some embodiments, contact 522 d is at least a source terminal of NMOS transistor N1 of memory cell 202[1,2] of FIG. 2 or memory cell 302[1,2] of FIG. 3.

Other quantities or configurations of the set of contacts 520 or 522 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more conductive structures 514 a, 514 c, 514 e (collectively referred to as a “set of conductive structures 514”) extending in at least the first direction X or the second direction Y. The set of conductive structures 514 is located on a fourth level. In some embodiments, the fourth level of memory circuit 500 is metal one (M1). In some embodiments, the M1 level is positioned above at least the active region, the M0 level, the POLY level or the MD level of memory circuit 500.

Conductive structures 514 a, 514 c are corresponding conductive structures 330 a, 330 c of FIG. 3. Conductive structure 514 e is source line SL1 of FIG. 3 or source line SL1 of FIG. 1.

In some embodiments, conductive structure 514 a is electrically coupled to at least a drain terminal of NMOS transistor N1 of memory circuit 500, memory cell 202[1,1] of FIG. 2 or memory cell 302[1,1] of FIG. 3 by contact 520 a.

In some embodiments, conductive structure 514 c is electrically coupled to at least a drain terminal of NMOS transistor N1 of memory circuit 500, memory cell 202[1,2] of FIG. 2 or memory cell 302[1,2] of FIG. 3 by at least contact 520 c.

In some embodiments, conductive structure 514 e is electrically coupled to at least a source terminal of NMOS transistor N1 of memory circuit 500, memory cell 202[1,1] of FIG. 2 or memory cell 302[1,1] of FIG. 3 by at least contact 522 a.

In some embodiments, conductive structure 514 e is electrically coupled to at least a source terminal of NMOS transistor N1 of memory circuit 500, memory cell 202[1,2] of FIG. 2 or memory cell 302[1,2] of FIG. 3 by at least contact 522 d.

Other quantities or configurations of the set of conductive structures 514 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more vias 530 a, 530 c (collectively referred to as a “set of vias 530”) and vias 532 a, 532 b, 532 d (collectively referred to as a “set of vias 532”). In some embodiments, set of vias 530 or 532 electrically couple the set of conductive structures 514 to upper metal layers (e.g., M2). In some embodiments, set of vias 530 or 532 is in the V1 level of memory circuit 500. The V1 level of memory circuit 500 is between the fourth level and a fifth level of memory circuit 500. Other quantities or configurations of the set of vias 530 or 532 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more conductive structures 524 a, 524 c, 524 e (collectively referred to as a “set of conductive structures 524”) extending in at least the first direction X or the second direction Y. The set of conductive structures 514 is located on a fifth level. In some embodiments, the fifth level of memory circuit 500 is metal two (M2). In some embodiments, the M2 level is positioned above at least the active region, the M0 level, the POLY level, the MD level or the M1 level of memory circuit 500.

In some embodiments, conductive structures 524 a, 524 c are corresponding conductive structures 330 a, 330 c of FIG. 3. In some embodiments, conductive structure 514 e is source line SL1 of FIG. 3 or source line SL1 of FIG. 1.

In some embodiments, conductive structure 524 a is electrically coupled to at least conductive structure 514 a by via 530 a.

In some embodiments, conductive structure 524 c is electrically coupled to at least conductive structure 514 c by via 530 c.

In some embodiments, conductive structure 524 e is electrically coupled to at least conductive structure 514 e by at least via 532 a or via 532 d. In some embodiments, conductive structures 514 e, 524 e located on two different metal levels corresponds to source line SL1 of memory circuit 300 or 500 or memory cell 100 of FIG. 1 resulting in less resistance than other approaches.

In some embodiments, memory circuit 500 includes a source line SL1 (e.g., either conductive structure 514 e or conductive structure 524 e) positioned on a single metal level.

Other quantities or configurations of the set of conductive structures 524 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more vias 538 a, 538 c (collectively referred to as a “set of vias 538”). In some embodiments, set of vias 538 electrically couple the set of conductive structures 524 to upper metal layers (e.g., M3). In some embodiments, set of vias 538 is in the V2 level of memory circuit 500. The V2 level of memory circuit 500 is between the fifth level and a sixth level of memory circuit 500. Other quantities or configurations of the set of vias 538 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more conductive structures 534 a, 534 c (collectively referred to as a “set of conductive structures 534”) and one or more conductive structures 536 a, 536 b (collectively referred to as a “set of conductive structures 536”) extending in at least the first direction X or the second direction Y.

The set of conductive structures 534 or 536 is located on a sixth level. In some embodiments, the sixth level of memory circuit 500 is metal three (M3). In some embodiments, the M3 level is positioned above at least the active region, the M0 level, the POLY level, the MD level, the M1 level or the M2 level of memory circuit 500.

The set of conductive structures 534 is set of conductive structures 330 of memory circuit 300. In some embodiments, conductive structures 534 a, 534 c are corresponding conductive structures 320 a, 320 c of FIG. 3.

Conductive structure 536 a is corresponding word line WL1 of memory cells 202[1,1] and 202[1,2] of FIG. 2 or memory cells 302[1,1] and 302[1,2] of FIG. 3. Conductive structure 536 b is corresponding word line WL2 of memory cells 202[2,1] and 202[2,2] of FIG. 2 or memory cells 302[2,1] and 302[2,2] of FIG. 3. In some embodiments, at least word line WL1 or word line WL2 is coupled to the corresponding gate 516 a, 516 b in a column (not shown) of memory circuit 500 that includes strap cells. In some embodiments, strap cells are memory cells configured to provide voltage pick-up and to provide N-well or P-well bias of the active region that prevents voltage drop along word lines WL that result in a difference in memory cell device voltages along the word lines WL as the word lines WL extend along memory cell array 200, memory circuit 300 or 500. In some embodiments, memory cell array 200 is surrounded by two columns of strap cells.

In some embodiments, conductive structure 534 a is electrically coupled to at least conductive structure 524 a by via 538 a. In some embodiments, conductive structure 534 c is electrically coupled to at least conductive structure 524 c by via 538 c.

Other quantities or configurations of the set of conductive structures 534 or 536 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more resistive switching elements 550 a, 550 c (hereinafter referred to as a “set of resistive switching elements 550”.)

The set of resistive switching elements 550 are set of resistive switching elements 350 of FIG. 3. In some embodiments, resistive switching elements 550 a, 550 c are corresponding resistive switching elements 350 a, 350 c of FIG. 3. At least one of the set of resistive switching elements 550 is resistive switching element 104 of FIG. 1.

The set of resistive switching elements 550 is located on a seventh level. In some embodiments, the seventh level of memory circuit 500 is above the M3 level and below the M4 level. In some embodiments, the seventh level is positioned above at least the active region, the M0 level, the POLY level, the MD level, the M1 level, the M2 level or the M3 level of memory circuit 500.

Resistive switching elements 550 a, 550 c include corresponding bottom electrodes 552 a, 552 c (collectively referred to as a “set of bottom electrodes 552”), corresponding resistive switching materials 554 a, 554 c (collectively referred to as a “set of resistive switching material 554”) and corresponding top electrodes 560 a, 560 c (collectively referred to as a “set of top electrodes 560.”)

At least one of the bottom electrodes of the set of bottom electrodes 552 corresponds to the bottom electrode 104 a of FIG. 1. Bottom electrodes 552 a, 552 c are above corresponding conductive structures 534 a, 534 c.

At least one of the resistive switching materials of the set of resistive switching materials 554 corresponds to resistive switching material 104 a of FIG. 1. Resistive switching materials 554 a, 554 c overlap at least a portion of corresponding conductive structures 534 a, 534 c. Resistive switching materials 554 a, 554 c overlap corresponding bottom electrodes 552 a, 552 c. Resistive switching materials 554 a, 554 c are above corresponding bottom electrodes 552 a, 552 c.

At least one of the top electrodes of the set of top electrodes 560 corresponds to top electrode 104 c of FIG. 1. Top electrodes 560 a, 560 c are above corresponding resistive switching materials 554 a, 554 c and corresponding bottom electrodes 552 a, 552 c.

Other configurations or quantities of elements in the set of resistive switching elements 550, set of bottom electrodes 552, set of resistive switching materials 554, set of top electrodes 560 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more conductive structures 540 a, 540 b (hereinafter referred to as a “set of conductive structures 540”) extending in the second direction Y.

The set of conductive structures 540 is located on an eighth level. In some embodiments, the eighth level of memory circuit 500 is metal four (M4). In some embodiments, the M4 level is positioned above at least the active region, the M0 level, the POLY level, the MD level, the M1 level, the M2 level or the M3 level of memory circuit 500.

Conductive structures 540 a, 540 b are corresponding bit lines BL1, BL2 of memory circuit 500. At least one conductive structure of the set of conductive structures 540 is bit line BL1 of FIG. 1. In some embodiments, conductive structure 540 a is at least conductive structure 340 a or 340 b of FIG. 3. In some embodiments, conductive structure 540 b is at least conductive structure 340 c or 340 d of FIG. 3. In some embodiments, conductive structures 540 a, 540 b are corresponding bit lines BL1, BL2 of FIG. 3.

Conductive structures 540 a, 540 b are above corresponding resistive switching elements 550 a, 550 c. Conductive structures 540 a, 540 b overlap corresponding resistive switching elements 550 a, 550 c. In some embodiments, set of conductive structures 540 is electrically coupled to the set of resistive switching elements 550. In some embodiments, conductive structures 540 a, 540 b is electrically coupled to corresponding top electrodes 560 a, 560 c. In some embodiments, set of conductive structures 540 is electrically coupled to the set of conductive structures 534 by the set of resistive switching elements 550. In some embodiments, conductive structures 540 a, 540 b is electrically coupled to corresponding conductive structures 534 a, 534 c by corresponding resistive switching elements 550 a, 550 c.

Other configurations or quantities of patterns in the set of conductive structures 540 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more vias 572 a, 572 b, 572 e, 572 f (collectively referred to as a “set of vias 572”). In some embodiments, set of vias 572 electrically couple the set of conductive structures 540 to upper metal layers (e.g., M5). In some embodiments, set of vias 572 is in the V4 level of memory circuit 500. The V4 level of memory circuit 500 is between an eighth level and a ninth level of memory circuit 500. Other quantities or configurations of the set of vias 572 are within the scope of the present disclosure.

Memory circuit 500 further includes one or more conductive structures 570 a, 570 b (hereinafter referred to as a “set of conductive structures 570”) extending in the second direction Y. The set of conductive structures 570 is located on a ninth level. In some embodiments, the ninth level of memory circuit 500 is metal five (M5). In some embodiments, the M5 level is positioned above at least the active region, the M0 level, the POLY level, the MD level, the M1 level, the M2 level, the M3 level or the M4 level of memory circuit 500.

In some embodiments, conductive structures 570 a, 570 b are corresponding bit lines BL1, BL2 of memory circuit 500. At least one conductive structure of the set of conductive structures 570 is bit line BL1 of FIG. 1. In some embodiments, conductive structures 570 a, 570 b are corresponding bit lines BL1, BL2 of FIG. 3.

In some embodiments, conductive structure 570 a is electrically coupled to at least conductive structure 540 a by at least via 572 a or 572 b.

In some embodiments, conductive structure 570 b is electrically coupled to at least conductive structure 540 b by at least via 572 e or 572 f.

In some embodiments, conductive structures 570 a, 540 a located on two different metal levels corresponds to bit line BL1 of memory circuit 300 or 500 or memory cell 100 of FIG. 1 resulting in less resistance than other approaches. In some embodiments, conductive structures 570 b, 540 b located on two different metal levels corresponds to bit line BL2 of memory circuit 300 or 500 or memory cell 100 of FIG. 1 resulting in less resistance than other approaches.

In some embodiments, a width of one of conductive structure 514 e, 524 e, 540 a, 540 b, 570 a or 570 b is the same as a width of another of conductive structure 514 e, 524 e, 540 a, 540 b, 570 a or 570 b. In some embodiments, a width of one of conductive structure 514 e, 524 e, 540 a, 540 b, 570 a or 570 b is different from a width of another of conductive structure 514 e, 524 e, 540 a, 540 b, 570 a or 570 b.

In some embodiments, a width of one of conductive structure 514 e, 524 e is the same as a width of one of conductive structure 540 a, 540 b, 570 a or 570 b resulting in less difference between the resistance of the bit lines BL1, BL2 and source lines SL1 compared with other approaches.

In some embodiments, memory circuit 500 includes a bit line BL1 (e.g., either conductive structure 540 a or conductive structure 570 a) positioned on a single metal level. In some embodiments, memory circuit 500 includes a bit line BL2 (e.g., either conductive structure 540 b or conductive structure 570 b) positioned on a single metal level.

Other configurations or quantities of patterns in the set of conductive structures 570 are within the scope of the present disclosure.

Method

FIG. 6 is a flowchart of a method 600 of forming or manufacturing a memory circuit in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method 600A depicted in FIG. 6, and that some other operations may only be briefly described herein. In some embodiments, the method 600 is usable to form memory circuits, such as memory cell 100 (FIG. 1), memory cell array 200 (FIG. 2), memory circuit 300 (FIG. 3) or memory circuit 500 (FIGS. 5A-5E). In some embodiments, the method 600 is usable to form memory circuits having similar structural relationships as one or more of layout design 400 (FIGS. 4A-4H).

In operation 602 of method 600, a layout design 400 of a memory circuit (e.g., memory cell 100, memory cell array 200, memory circuit 300 or 500) is generated. Operation 602 is performed by a processing device (e.g., processor 802 (FIG. 8)) configured to execute instructions for generating a layout design 400. In some embodiments, the layout design 400 is a graphic database system (GDSII) file format.

In operation 604 of method 600, the memory circuit (e.g., memory cell 100, memory cell array 200, memory circuit 300 or 500) is manufactured based on layout design 400. In some embodiments, operation 604 of method 600 comprises manufacturing at least one mask based on the layout design 400, and manufacturing the memory circuit (e.g., memory cell 100, memory cell array 200, memory circuit 300 or 500) based on the at least one mask.

FIG. 7 is a flowchart of a method 700 of generating a layout design of a memory circuit in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method 700 depicted in FIG. 7, and that some other processes may only be briefly described herein. In some embodiments, the method 700 is usable to generate one or more layout patterns of layout design 400 (FIGS. 4A-4H) of a memory circuit (e.g., memory cell 100, memory cell array 200, memory circuit 300 or 500).

In operation 702 of method 700, a first set of memory cell layout patterns (e.g., memory cell layout pattern 402[1,1] or 402[2,1]) is generated or placed on layout design 400. In some embodiments, the first set of memory cell layout patterns corresponds to fabricating a first set of memory cells (e.g., memory cells 302[1,1] or 302[2,1] or memory cell 502 a) arranged in a first column (e.g., column 1) of memory cells. In some embodiments, each of the layout patterns of the first of memory cell layout patterns is separated from an adjacent layout pattern of the first set of memory cell layout patterns in second direction Y.

In some embodiments, operation 702 comprises at least operation 702 a (not shown) or operation 702 b (not shown).

In some embodiments, operation 702 a comprises generating or placing a set of selector element layout patterns (e.g., selector element layout pattern 404 a, 404 b) on layout design 400. In some embodiments, selector element layout patterns layout patterns 404 a, 404 b) correspond to fabricating selector elements 314 a, 314 b arranged in the first column (e.g., column 1) of memory cells. In some embodiments, each of the layout patterns of the set of selector element layout patterns is separated from an adjacent layout pattern of the set of selector element in the second direction Y and is located on a first set of layout levels (e.g., layout levels OD-M1).

In some embodiments, operation 702 b comprises generating or placing a set of resistive switching element layout patterns (e.g., resistive switching element layout patterns 450 a, 450 b) on layout design 400. In some embodiments, set of resistive switching element layout patterns (e.g., resistive switching element layout patterns 450 a, 450 b) corresponds to fabricating a set of resistive switching elements 350 or 550 arranged in the first column (e.g., column 1) of memory cells. In some embodiments, each of the layout patterns of the set of resistive switching element layout patterns is separated from an adjacent layout pattern of the set of resistive switching element layout patterns in the second direction Y, and is located on a second set of layout levels (e.g., layout levels M3-M4) above the first set of layout levels.

In operation 704 of method 700, a second set of memory cell layout patterns (e.g., memory cell layout pattern 402[1,2] or 402[2,2]) is generated or placed on layout design 400. In some embodiments, the second set of memory cell layout patterns corresponds to fabricating a second set of memory cells (e.g., memory cells 302[1,2] or 302[2,2] or memory cell 502 b) arranged in a second column (e.g., column 2) of memory cells. In some embodiments, each of the layout patterns of the second set of memory cell layout patterns is separated from an adjacent layout pattern of the second set of memory cell layout patterns in second direction Y.

In some embodiments, operation 704 comprises at least operation 704 a (not shown) or operation 704 b (not shown).

In some embodiments, operation 704 a comprises generating or placing a set of selector element layout patterns (e.g., selector element layout pattern 404 c, 404 d) on layout design 400. In some embodiments, selector element layout patterns layout patterns 404 c, 404 d) correspond to fabricating selector elements 314 c, 314 d arranged in the second column (e.g., column 2) of memory cells. In some embodiments, each of the layout patterns of the set of selector element layout patterns is separated from an adjacent layout pattern of the set of selector element in the second direction Y and is located on the first set of layout levels (e.g., layout levels OD-M1).

In some embodiments, operation 704 b comprises generating or placing a set of resistive switching element layout patterns (e.g., resistive switching element layout patterns 450 c, 450 d) on layout design 400. In some embodiments, set of resistive switching element layout patterns (e.g., resistive switching element layout patterns 450 c, 450 d) corresponds to fabricating a set of resistive switching elements 350 or 550 arranged in the second column (e.g., column 2) of memory cells. In some embodiments, each of the layout patterns of the set of resistive switching element layout patterns is separated from an adjacent layout pattern of the set of resistive switching element layout patterns in the second direction Y, and is located on the second set of layout levels (e.g., layout levels M3-M4).

In some embodiments, at least operation 702 b or 704 b comprises at least operation 705 a (not shown), operation 705 b (not shown) or operation 705 c (not shown).

In some embodiments, operation 705 a comprises generating or placing a bottom electrode element layout pattern 452 a, 452 b, 452 c or 452 d on layout level BE. In some embodiments, bottom electrode element layout pattern 452 a, 452 b, 452 c or 452 d corresponds to fabricating bottom electrode element 104 a, 552 a or 552 c.

In some embodiments, operation 705 b comprises generating or placing a resistive switching material layout pattern 454 a, 454 b, 454 c or 454 d on layout level TMO. In some embodiments, resistive switching material layout pattern 454 a, 454 b, 454 c or 454 d corresponds to fabricating resistive switching material 104 b, 554 a or 554 c.

In some embodiments, operation 705 c comprises generating or placing a top electrode element layout pattern 460 a, 460 b, 460 c or 460 d on layout level TE. In some embodiments, top electrode element layout pattern 452 a, 452 b, 452 c or 452 d corresponds to fabricating top electrode element 104 c, 560 a or 560 c.

In some embodiments, operation 706 comprises generating or placing a source line layout pattern (e.g., at least conductive feature layout pattern 414 e or 424 e) on layout design 400.

In some embodiments, operation 706 comprises at least operation 706 a (not shown).

In some embodiments, operation 706 a comprises generating or placing a first set of conductive feature layout patterns (e.g., conductive feature layout pattern 414 e) extending in the second direction Y. In some embodiments, conductive feature layout pattern 414 e is positioned between the first set of memory cell layout patterns and the second set of memory cell layout patterns. In some embodiments, the first set of conductive feature layout patterns (e.g., conductive feature layout pattern 414 e) corresponds to fabricating a source line SL1 in FIGS. 1-3 and 5 that extends in the second direction Y and is coupled to the first set of memory cells and the second set of memory cells. In some embodiments, the first set of conductive feature layout patterns (e.g., conductive feature layout pattern 414 e) is located on the M1 layout level.

In some embodiments, operation 706 further comprises at least operation 706 b (not shown) or operation 706 c (not shown).

In some embodiments, operation 706 b comprises generating or placing a second set of conductive feature layout patterns (e.g., conductive feature layout pattern 424 e) extending in the second direction Y. In some embodiments, conductive feature layout pattern 424 e is positioned between the first set of memory cell layout patterns and the second set of memory cell layout patterns. In some embodiments, the second set of conductive feature layout patterns (e.g., conductive feature layout pattern 424 e) corresponds to fabricating source line SL1 in FIGS. 1-3 and 5 that extends in the second direction Y and is coupled to the first set of memory cells and the second set of memory cells. In some embodiments, the second set of conductive feature layout patterns (e.g., conductive feature layout pattern 424 e) is located on the M2 layout level different from the M1 layout level.

In some embodiments, operation 706 c comprises generating or placing a set of via layout patterns (e.g., set of via layout patterns 422) on layout design 400. In some embodiments, the set of via layout patterns is located between the M1 layout level and the M2 layout level. In some embodiments, the set of via layout patterns (e.g., set of via layout patterns 422) corresponds to fabricating a set of vias 522 coupled between the source line SL1 and another portion of the source line SL1. In some embodiments, set of vias 522 are coupled between conductive feature layout pattern 424 e and conductive feature layout pattern 414 e.

In some embodiments, operation 708 comprises generating or placing a first bit line layout pattern (e.g., at least conductive feature layout pattern 440 a) on layout design 400.

In some embodiments, operation 708 comprises at least operation 708 a (not shown).

In some embodiments, operation 708 a comprises generating or placing a third set of conductive feature layout patterns (e.g., conductive feature layout pattern 440 a) extending in the second direction Y. In some embodiments, the third set of conductive feature layout patterns (e.g., conductive feature layout pattern 440 a) is located on a M4 layout level. In some embodiments, the third set of conductive feature layout patterns (e.g., conductive feature layout pattern 440 a) corresponds to fabricating a first portion (e.g., 540 a) of a first bit line BL1 coupled to the first set of memory cells.

In some embodiments, operation 708 further comprises at least operation 708 b or 708 c.

In some embodiments, operation 708 a comprises generating or placing a fourth set of conductive feature layout patterns (e.g., conductive feature layout pattern 470 a) extending in the second direction Y. In some embodiments, the fourth set of conductive feature layout patterns (e.g., conductive feature layout pattern 470 a) is located on a M5 layout level. In some embodiments, the fourth set of conductive feature layout patterns (e.g., conductive feature layout pattern 470 a) corresponds to fabricating a second portion (e.g., 570 a) of the first bit line BL1 coupled to the first set of memory cells.

In some embodiments, operation 708 b comprises generating or placing a set of via layout patterns (e.g., via layout patterns 472 a, 427 b, 472 c, 472 d) between the third set of conductive feature layout patterns (e.g., conductive feature layout pattern 470 a) and the fourth set of conductive feature layout patterns (e.g., conductive feature layout pattern 440 a). In some embodiments, the set of via layout patterns (e.g., via layout patterns 472 a, 427 b, 472 c, 472 d) corresponds to fabricating vias 572 a, 572 b coupled between the first portion of the first bit line BL1 and the second portion of the first bit line BL1.

In some embodiments, operation 710 comprises generating or placing a second bit line layout pattern (e.g., at least conductive feature layout pattern 440 b) on layout design 400.

In some embodiments, operation 710 comprises at least operation 710 a (not shown).

In some embodiments, operation 710 a comprises generating or placing a fifth set of conductive feature layout patterns (e.g., conductive feature layout pattern 440 c) extending in the second direction Y. In some embodiments, the fifth set of conductive feature layout patterns (e.g., conductive feature layout pattern 440 c) is located on the M4 layout level. In some embodiments, the fifth set of conductive feature layout patterns (e.g., conductive feature layout pattern 440 c) corresponds to fabricating a first portion (e.g., 540 b) of a second bit line BL2 coupled to the second set of memory cells.

In some embodiments, operation 710 further comprises at least operation 710 b or 710 c.

In some embodiments, operation 710 a comprises generating or placing a sixth set of conductive feature layout patterns (e.g., conductive feature layout pattern 470 b) extending in the second direction Y. In some embodiments, the sixth set of conductive feature layout patterns (e.g., conductive feature layout pattern 470 b) is located on the M5 layout level. In some embodiments, the sixth set of conductive feature layout patterns (e.g., conductive feature layout pattern 470 b) corresponds to fabricating a second portion (e.g., 570 b) of the second bit line BL2 coupled to the second set of memory cells.

In some embodiments, operation 710 b comprises generating or placing a set of via layout patterns (e.g., via layout patterns 472 e, 427 f, 472 g, 472 h) between the sixth set of conductive feature layout patterns (e.g., conductive feature layout pattern 470 b) and the fifth set of conductive feature layout patterns (e.g., conductive feature layout pattern 440 b). In some embodiments, the set of via layout patterns (e.g., via layout patterns 472 e, 427 f, 472 g, 472 h) corresponds to fabricating vias 572 e, 572 f coupled between the first portion of the second bit line BL2 and the second portion of the second bit line BL2.

In some embodiments, layout design 400 is a standard cell. In some embodiments, one or more of operations 702, 704, 706, 708 or 710 is not performed.

One or more of the operations of methods 600-700 is performed by a processing device configured to execute instructions for manufacturing a memory circuit, such as memory circuit 100, 300 or 500, or a memory array, such as memory array 200. In some embodiments, one or more operations of methods 600-700 is performed using a same processing device as that used in a different one or more operations of methods 600-700. In some embodiments, a different processing device is used to perform one or more operations of methods 600-700 from that used to perform a different one or more operations of methods 600-700.

FIG. 8 is a schematic view of a system 800 for designing an IC layout design in accordance with some embodiments. In some embodiments, system 800 generates or places one or more IC layout designs described herein. System 800 includes a hardware processor 802 and a non-transitory, computer readable storage medium 804 encoded with, i.e., storing, the computer program code 806, i.e., a set of executable instructions. Computer readable storage medium 804 is configured for interfacing with manufacturing machines for producing the integrated circuit. The processor 802 is electrically coupled to the computer readable storage medium 804 via a bus 808. The processor 802 is also electrically coupled to an I/O interface 810 by bus 808. A network interface 812 is also electrically connected to the processor 802 via bus 808. Network interface 812 is connected to a network 814, so that processor 802 and computer readable storage medium 804 are capable of connecting to external elements via network 814. The processor 802 is configured to execute the computer program code 806 encoded in the computer readable storage medium 804 in order to cause system 800 to be usable for performing a portion or all of the operations as described in method 600 or 700.

In some embodiments, the processor 802 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In some embodiments, the computer readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, the computer readable storage medium 804 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In some embodiments using optical disks, the computer readable storage medium 804 includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).

In some embodiments, the storage medium 804 stores the computer program code 806 configured to cause system 800 to perform method 600 or 700. In some embodiments, the storage medium 804 also stores information needed for performing method 600 or 700 as well as information generated during performing method 600 or 700, such as layout design 816 and user interface 818, and/or a set of executable instructions to perform the operation of method 600 or 700. In some embodiments, layout design 816 comprises one or more of layout patterns of layout design 400.

In some embodiments, the storage medium 804 stores instructions (e.g., computer program code 806) for interfacing with manufacturing machines. The instructions (e.g., computer program code 806) enable processor 802 to generate manufacturing instructions readable by the manufacturing machines to effectively implement method 600 or 700 during a manufacturing process.

System 800 includes I/O interface 810. I/O interface 810 is coupled to external circuitry. In some embodiments, I/O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, and/or cursor direction keys for communicating information and commands to processor 802.

System 800 also includes network interface 812 coupled to the processor 802. Network interface 812 allows system 800 to communicate with network 814, to which one or more other computer systems are connected. Network interface 812 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interface such as ETHERNET, USB, or IEEE-1394. In some embodiments, method 600 or 700 is implemented in two or more systems 800, and information such as layout design, and user interface are exchanged between different systems 800 by network 814.

System 800 is configured to receive information related to a layout design through I/O interface 810 or network interface 812. The information is transferred to processor 802 by bus 808 to determine a layout design for producing IC 100A-100B or 400. The layout design is then stored in computer readable medium 804 as layout design 816. System 800 is configured to receive information related to a user interface through I/O interface 810 or network interface 812. The information is stored in computer readable medium 804 as user interface 818.

In some embodiments, method 600 or 700 is implemented as a standalone software application for execution by a processor. In some embodiments, method 600 or 700 is implemented as a software application that is a part of an additional software application. In some embodiments, method 600 or 700 is implemented as a plug-in to a software application. In some embodiments, method 600 or 700 is implemented as a software application that is a portion of an EDA tool. In some embodiments, method 600 or 700 is implemented as a software application that is used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of the integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer readable medium. In some embodiments, the layout is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the layout is generated based on a netlist which is created based on the schematic design. In some embodiments, method 600 or 700 is implemented by a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs generated by system 800. In some embodiments, system 800 a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs of the present disclosure. In some embodiments, system 800 of FIG. 8 generates layout designs of an integrated circuit that are smaller than other approaches. In some embodiments, system 800 of FIG. 8 generates layout designs of integrated circuit structure that occupy less area and provide better routing resources than other approaches.

FIG. 9 is a block diagram of an integrated circuit (IC) manufacturing system 900, and an IC manufacturing flow associated therewith, in accordance with at least one embodiment of the present disclosure.

In FIG. 9, IC manufacturing system 900 includes entities, such as a design house 920, a mask house 940, and an IC manufacturer/fabricator (“fab”) 940, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device 960. The entities in system 900 are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house 920, mask house 940, and IC fab 940 is owned by a single larger company. In some embodiments, two or more of design house 920, mask house 940, and IC fab 940 coexist in a common facility and use common resources.

Design house (or design team) 920 generates an IC design layout 922. IC design layout 922 includes various geometrical patterns designed for an IC device 960. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device 960 to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout 922 includes various IC features, such as an active region, gate electrode, source electrode and drain electrode, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house 920 implements a proper design procedure to form IC design layout 922. The design procedure includes one or more of logic design, physical design or place and route. IC design layout 922 is presented in one or more data files having information of the geometrical patterns. For example, IC design layout 922 can be expressed in a GDSII file format or DFII file format.

Mask house 940 includes data preparation 952 and mask fabrication 944. Mask house 940 uses IC design layout 922 to manufacture one or more masks to be used for fabricating the various layers of IC device 960 according to IC design layout 922. Mask house 940 performs mask data preparation 952, where IC design layout 922 is translated into a representative data file (“RDF”). Mask data preparation 952 provides the RDF to mask fabrication 944. Mask fabrication 944 includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by mask data preparation 952 to comply with particular characteristics of the mask writer and/or requirements of IC fab 940. In FIG. 9, mask data preparation 952 and mask fabrication 944 are illustrated as separate elements. In some embodiments, mask data preparation 952 and mask fabrication 944 can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation 952 includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout 922. In some embodiments, mask data preparation 952 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation 952 includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during mask fabrication 944, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation 952 includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab 940 to fabricate IC device 960. LPC simulates this processing based on IC design layout 922 to create a simulated manufactured device, such as IC device 960. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout 922.

It should be understood that the above description of mask data preparation 952 has been simplified for the purposes of clarity. In some embodiments, data preparation 952 includes additional features such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to IC design layout 922 during data preparation 952 may be executed in a variety of different orders.

After mask data preparation 952 and during mask fabrication 944, a mask or a group of masks are fabricated based on the modified IC design layout. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask can be formed in various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using a phase shift technology. In the phase shift mask (PSM), various features in the pattern formed on the mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication 944 is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etching regions in the semiconductor wafer, and/or in other suitable processes.

IC fab 940 is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab 940 is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.

IC fab 940 uses the mask (or masks) fabricated by mask house 940 to fabricate IC device 960. Thus, IC fab 940 at least indirectly uses IC design layout 922 to fabricate IC device 960. In some embodiments, a semiconductor wafer 952 is fabricated by IC fab 940 using the mask (or masks) to form IC device 960. Semiconductor wafer 952 includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g., system 900 of FIG. 9), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference.

It will be readily seen by one of ordinary skill in the art that one or more of the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.

One aspect of this description relates to a method of forming a memory cell array. The method includes generating, by a processor, a layout design of the memory cell array and manufacturing the memory cell array based on the layout design. In some embodiments, the generating of the layout design of the memory cell array includes generating a first set of memory cell layout patterns that corresponds to fabricating a first set of memory cells arranged in a first column of memory cells. In some embodiments, each of the layout patterns of the first of memory cell layout patterns is separated from an adjacent layout pattern of the first set of memory cell layout patterns in a first direction. In some embodiments, the generating of the layout design of the memory cell array further includes generating a second set of memory cell layout patterns that corresponds to fabricating a second set of memory cells arranged in a second column of memory cells. In some embodiments, the second set of memory cell layout patterns is separated from the first set of memory cell layout patterns in a second direction different from the first direction. In some embodiments, each of the layout patterns of the second of memory cell layout patterns is separated from an adjacent layout pattern of the second set of memory cell layout patterns in the first direction. In some embodiments, the generating of the layout design of the memory cell array further includes generating a first set of conductive feature layout patterns extending in the first direction. In some embodiments, a layout pattern of the first set of conductive feature layout patterns is positioned between the first set of memory cell layout patterns and the second set of memory cell layout patterns. In some embodiments, the first set of conductive feature layout patterns corresponds to fabricating a source line extending in the first direction and being coupled to the first set of memory cells and the second set of memory cells. In some embodiments, the generating the layout design of the memory cell array further includes generating a second set of conductive feature layout patterns extending in the first direction. In some embodiments, the second set of conductive feature layout patterns is located on a first layout level. In some embodiments, the second set of conductive feature layout patterns corresponds to fabricating a first portion of a first bit line coupled to the first set of memory cells. In some embodiments, the generating the layout design of the memory cell array further includes generating a third set of conductive feature layout patterns extending in the first direction. In some embodiments, the third set of conductive feature layout patterns is located on the first layout level. In some embodiments, the third set of conductive feature layout patterns is separated from the second set of conductive feature layout patterns in the second direction. In some embodiments, the third set of conductive feature layout patterns corresponds to fabricating a first portion of a second bit line coupled to the second set of memory cells. In some embodiments, the generating the layout design of the memory cell array further includes generating a fourth set of conductive feature layout patterns extending in the first direction. In some embodiments, the fourth set of conductive feature layout patterns is located on a second layout level different from the first layout level. In some embodiments, the fourth set of conductive feature layout patterns corresponds to fabricating a second portion of the first bit line. In some embodiments, the generating the layout design of the memory cell array further includes generating a fifth set of conductive feature layout patterns extending in the first direction. In some embodiments, the fifth set of conductive feature layout patterns is located on the second layout level. In some embodiments, the fifth set of conductive feature layout patterns is separated from the fourth set of conductive feature layout patterns in the second direction. In some embodiments, the fifth set of conductive feature layout patterns corresponds to fabricating a second portion of the second bit line. In some embodiments, the generating the layout design of the memory cell array further includes generating a first set of via layout patterns. In some embodiments, the first set of via layout patterns is located between the second layout level and the first layout level. In some embodiments, the first set of via layout patterns corresponds to fabricating vias coupled between the first portion of the first bit line and the second portion of the first bit line. In some embodiments, the generating the layout design of the memory cell array further includes generating a second set of via layout patterns. In some embodiments, the second set of via layout patterns is located between the second layout level and the first layout level. In some embodiments, the second set of via layout patterns corresponds to fabricating vias coupled between the first portion of the second bit line and the second portion of the second bit line. In some embodiments, the generating the layout design of the memory cell array further includes generating a second set of conductive feature layout patterns extending in the first direction. In some embodiments, the second set of conductive feature layout patterns is located on a second layout level different from the first layout level. In some embodiments, the second set of conductive feature layout patterns corresponds to fabricating another portion of the source line. In some embodiments, the generating the layout design of the memory cell array further includes generating a set of via layout patterns. In some embodiments, the set of via layout patterns is located between the second layout level and the first layout level. In some embodiments, the set of via layout patterns corresponds to fabricating vias coupled between the source line and another portion of the source line. In some embodiments, the generating the first set of memory cell layout patterns or the second set of memory cell layout patterns includes generating a set of selector element layout patterns that corresponds to fabricating a set of selector elements arranged in the first column or the second column of memory cells. In some embodiments, each of the layout patterns of the set of selector element layout patterns is separated from an adjacent layout pattern of the set of selector element in the first direction and is located on a first set of layout levels. In some embodiments, the generating the first set of memory cell layout patterns or the second set of memory cell layout patterns further includes generating a set of resistive switching element layout patterns that corresponds to fabricating a set of resistive switching elements arranged in the first column or the second column of memory cells. In some embodiments, each of the layout patterns of the set of resistive switching element layout patterns is separated from an adjacent layout pattern of the set of resistive switching element layout patterns in the first direction, and is located on a second set of layout levels above the first set of layout levels. In some embodiments, the generating the set of resistive switching element layout patterns includes generating a bottom electrode element layout pattern that corresponds to fabricating a bottom electrode element. In some embodiments, the bottom electrode element layout pattern is located on a first layout level. In some embodiments the generating the set of resistive switching element layout patterns further includes generating a resistive switching material layout pattern that corresponds to fabricating a resistive switching material. In some embodiments, the resistive switching material layout pattern is located on a second layout level different from the first layout level. In some embodiments the generating the set of resistive switching element layout patterns further includes generating a top electrode element layout pattern that corresponds to fabricating a top electrode element. In some embodiments, the top electrode element layout pattern is located on a third layout level different from the first layout level and the second layout level.

Another aspect of this description relates to a memory cell array. The memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line, a source line and a first set of vias. In some embodiments, the second column of memory cells is separated from the first column of memory cells in a first direction, the first column of memory cells and the second column of memory cells being arranged in a second direction different from the first direction. In some embodiments, the first bit line is coupled to the first column of memory cells, and extending in the second direction. In some embodiments, the second bit line is coupled to the second column of memory cells, and extends in the second direction. In some embodiments, the first bit line or the second bit line includes a first conductive line extending in the second direction, and being located on a first metal layer; and a second conductive line extending in the second direction, and being located on a second metal layer above the first metal layer. In some embodiments, the first conductive line and the second conductive line overlap a source of a transistor of a memory cell of the first column of memory cells or the second column of memory cells. In some embodiments, the source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells. In some embodiments, the first set of vias is electrically coupled to the first conductive line and the second conductive line, and is between the first conductive line and the second conductive line. In some embodiments, a pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first column of memory cells or the second column of memory cells. In some embodiments, each memory cell of the first column of memory cells or the second column of memory cells is a non-volatile memory cell. In some embodiments, the non-volatile memory cell includes one or more of a resistance random access memory (RRAM), a ferroelectric RAM (FRAM) or a Magnetoresistive RAM (MRAM). In some embodiments, a resistance of the first bit line or a resistance of the second bit line is substantially equal to a resistance of the source line. In some embodiments, the source line includes a first conductive line extending in the second direction, and being located on a first metal layer. In some embodiments, the source line further includes a second conductive line and a set of vias. The second conductive line extends in the second direction, and is located on a second metal layer above the first metal layer. The set of vias is electrically coupled to the first conductive line and the second conductive line, and is located between the first conductive line and the second conductive line. In some embodiments, the first metal layer is a metal 1 (M1) layer, and the second metal layer is a metal 2 (M2) layer. In some embodiments, the first bit line or the second bit line includes a first conductive line extending in the second direction, and being located on a first metal layer. In some embodiments, the first bit line or the second bit line further includes a second conductive line and a set of vias. The second conductive line extends in the second direction, and is located on a second metal layer above the first metal layer. The set of vias is electrically coupled to the first conductive line and the second conductive line, and is located between the first conductive line and the second conductive line. In some embodiments, the first metal layer is a metal 4 (M4) layer, and the second metal layer is a metal 5 (M5) layer.

Still another aspect of this description relates to a method of forming a memory cell array. The method includes generating, by a processor, a layout design of the memory cell array and manufacturing the memory cell array based on the layout design. In some embodiments, the generating of the layout design of the memory cell array includes placing a first set of memory cell layout patterns in a first column, the first set of memory cell layout patterns corresponding to fabricating a first set of memory cells, each layout pattern of the first set of memory cell layout patterns being separated from an adjacent layout pattern of the first set of memory cell layout patterns in a first direction. In some embodiments, the generating of the layout design of the memory cell array further includes placing a second set of memory cell layout patterns in a second column separated from the first column in a second direction different from the first direction, the second set of memory cell layout patterns corresponding to fabricating a second set of memory cells, each layout pattern of the second set of memory cell layout patterns being separated from an adjacent layout pattern of the second set of memory cell layout patterns in the first direction. In some embodiments, the generating of the layout design of the memory cell array further includes placing a first set of conductive feature layout patterns in the first column, the first set of conductive feature layout patterns extending in the first direction and overlapping the first set of memory cell layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a first bit line extending in the first direction and being coupled to the first set of memory cells. In some embodiments, the generating of the layout design of the memory cell array further includes placing a second set of conductive feature layout patterns in the second column, the second set of conductive feature layout patterns extending in the first direction and overlapping the second set of memory cell layout patterns, the second set of conductive feature layout patterns corresponding to fabricating a second bit line extending in the first direction and being coupled to the second set of memory cells. In some embodiments, the placing the first set of conductive feature layout patterns includes placing a first conductive feature layout pattern on a first layout level, the first conductive feature layout pattern extending in the first direction, and the first conductive feature layout pattern corresponding to fabricating a first portion of the first bit line coupled to the first set of memory cells. In some embodiments, the placing the first set of conductive feature layout patterns further includes placing a second conductive feature layout pattern on a second layout level different from the first layout level, the second conductive feature layout pattern extending in the first direction, and the second conductive feature layout pattern corresponding to fabricating a second portion of the first bit line coupled to the first set of memory cells. In some embodiments, the generating the layout design of the memory cell array further includes placing a first set of via layout patterns between the first layout level and the second layout level, and the first set of via layout patterns corresponding to fabricating vias coupled between the first portion of the first bit line and the second portion of the first bit line. In some embodiments, the generating the layout design of the memory cell array further includes placing a third set of conductive feature layout patterns between the first set of memory cell layout patterns and the second set of memory cell layout patterns, the third set of conductive feature layout patterns extending in the first direction, the third set of conductive feature layout patterns corresponding to fabricating a source line extending in the first direction and being coupled to the first set of memory cells and the second set of memory cells. In some embodiments, the placing the third set of conductive feature layout patterns between the first set of memory cell layout patterns and the second set of memory cell layout patterns includes placing a first conductive feature layout pattern on a first layout level, the first conductive feature layout pattern extending in the first direction, and the first conductive feature layout pattern corresponding to fabricating a first portion of the source line coupled to the first set of memory cells and the second set of memory cells. In some embodiments, the placing the third set of conductive feature layout patterns between the first set of memory cell layout patterns and the second set of memory cell layout patterns further includes placing a second conductive feature layout pattern on a second layout level different from the first layout level, the second conductive feature layout pattern extending in the first direction, and the second conductive feature layout pattern corresponding to fabricating a second portion of the source line coupled to the first set of memory cells and the second set of memory cells. In some embodiments, the generating the layout design of the memory cell array further includes placing a first set of via layout patterns between the first layout level and the second layout level, and the first set of via layout patterns corresponding to fabricating vias coupled between the first portion of the source line and the second portion of the source line. In some embodiments, the placing the first set of memory cell layout patterns or the second set of memory cell layout patterns includes placing a first selector element layout pattern in the first column or the second column, the first selector element layout pattern corresponding to fabricating a first selector element, the first selector element layout pattern being located on a first set of layout levels. In some embodiments, the placing the first set of memory cell layout patterns or the second set of memory cell layout patterns further includes placing a first electrode element layout pattern on a first layout level, the first electrode element layout pattern corresponding to fabricating a bottom electrode element of a resistive switching element, the resistive switching element being coupled to the first selector element. In some embodiments, the placing the first set of memory cell layout patterns or the second set of memory cell layout patterns further includes placing a second electrode element layout pattern on a second layout level different from the first layout level, the second electrode element layout pattern corresponding to fabricating a top electrode element of the resistive switching element. In some embodiments, the placing the first set of memory cell layout patterns or the second set of memory cell layout patterns further includes placing a resistive switching material layout pattern between the first layout level and the second layout level, the resistive switching material layout pattern corresponding to fabricating a resistive switching material of the resistive switching element.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A method of forming a memory cell array, the method comprising: generating, by a processor, a layout design of the memory cell array, wherein the generating of the layout design comprises: generating a first set of memory cell layout patterns corresponding to fabricating a first set of memory cells arranged in a first column of memory cells, each layout pattern of the first set of memory cell layout patterns being separated from an adjacent layout pattern of the first set of memory cell layout patterns in a first direction; generating a second set of memory cell layout patterns corresponding to fabricating a second set of memory cells arranged in a second column of memory cells, the second set of memory cell layout patterns being separated from the first set of memory cell layout patterns in a second direction different from the first direction, each layout pattern of the second set of memory cell layout patterns being separated from an adjacent layout pattern of the second set of memory cell layout patterns in the first direction; generating a first set of conductive feature layout patterns extending in the first direction, a layout pattern of the first set of conductive feature layout patterns being positioned between the first set of memory cell layout patterns and the second set of memory cell layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a source line extending in the first direction and being coupled to the first set of memory cells and the second set of memory cells; and manufacturing the memory cell array based on the layout design.
 2. The method of claim 1, wherein the generating the layout design of the memory cell array further comprises: generating a second set of conductive feature layout patterns extending in the first direction, the second set of conductive feature layout patterns being located on a first layout level, and the second set of conductive feature layout patterns corresponding to fabricating a first portion of a first bit line coupled to the first set of memory cells; and generating a third set of conductive feature layout patterns extending in the first direction, the third set of conductive feature layout patterns being located on the first layout level, the third set of conductive feature layout patterns being separated from the second set of conductive feature layout patterns in the second direction, the third set of conductive feature layout patterns corresponding to fabricating a first portion of a second bit line coupled to the second set of memory cells.
 3. The method of claim 2, wherein the generating the layout design of the memory cell array further comprises: generating a fourth set of conductive feature layout patterns extending in the first direction, the fourth set of conductive feature layout patterns being located on a second layout level different from the first layout level, and the fourth set of conductive feature layout patterns corresponding to fabricating a second portion of the first bit line; generating a fifth set of conductive feature layout patterns extending in the first direction, the fifth set of conductive feature layout patterns being located on the second layout level, the fifth set of conductive feature layout patterns being separated from the fourth set of conductive feature layout patterns in the second direction, the fifth set of conductive feature layout patterns corresponding to fabricating a second portion of the second bit line; generating a first set of via layout patterns, the first set of via layout patterns being located between the second layout level and the first layout level, and the first set of via layout patterns corresponding to fabricating vias coupled between the first portion of the first bit line and the second portion of the first bit line; and generating a second set of via layout patterns, the second set of via layout patterns being located between the second layout level and the first layout level, and the second set of via layout patterns corresponding to fabricating vias coupled between the first portion of the second bit line and the second portion of the second bit line.
 4. The method of claim 1, wherein the generating the layout design of the memory cell array further comprises: generating a second set of conductive feature layout patterns extending in the first direction, the second set of conductive feature layout patterns being located on a first layout level and a second layout level different from the first layout level, and the second set of conductive feature layout patterns corresponding to fabricating another portion of the source line; and generating a set of via layout patterns, the set of via layout patterns being located between the second layout level and the first layout level, and the set of via layout patterns corresponding to fabricating vias coupled between the source line and the another portion of the source line.
 5. The method of claim 1, wherein the generating the first set of memory cell layout patterns or the second set of memory cell layout patterns comprises: generating a set of selector element layout patterns corresponding to fabricating a set of selector elements arranged in the first column of memory cells or the second column of memory cells, each layout pattern of the set of selector element layout patterns being separated from an adjacent layout pattern of the set of selector element in the first direction and being located on a first set of layout levels; and generating a set of resistive switching element layout patterns corresponding to fabricating a set of resistive switching elements arranged in the first column of memory cells or the second column of memory cells, each layout pattern of the set of resistive switching element layout patterns being separated from an adjacent layout pattern of the set of resistive switching element layout patterns in the first direction, and being located on a second set of layout levels above the first set of layout levels.
 6. The method of claim 5, wherein the generating the set of resistive switching element layout patterns comprises: generating a bottom electrode element layout pattern corresponding to fabricating a bottom electrode element, the bottom electrode element layout pattern being located on a first layout level; generating a resistive switching material layout pattern corresponding to fabricating a resistive switching material, the resistive switching material layout pattern being located on a second layout level different from the first layout level; and generating a top electrode element layout pattern corresponding to fabricating a top electrode element, the top electrode element layout pattern being located on a third layout level different from the first layout level and the second layout level.
 7. A memory cell array comprising: a first column of memory cells; a second column of memory cells being separated from the first column of memory cells in a first direction, the first column of memory cells and the second column of memory cells being arranged in a second direction different from the first direction; a first bit line coupled to the first column of memory cells, and extending in the second direction; a second bit line coupled to the second column of memory cells, and extending in the second direction, the first bit line or the second bit line comprises: a first conductive line extending in the second direction, and being located on a first metal layer; and a second conductive line extending in the second direction, and being located on a second metal layer above the first metal layer, the first conductive line and the second conductive line overlap a source of a transistor of a memory cell of the first column of memory cells or the second column of memory cells; a source line extending in the second direction, being coupled to the first column of memory cells and the second column of memory cells; and a first set of vias electrically coupled to the first conductive line and the second conductive line, and being between the first conductive line and the second conductive line, a pair of vias of the first set of vias being located above where the first conductive line overlaps each memory cell of the first column of memory cells or the second column of memory cells.
 8. The memory cell array of claim 7, wherein each memory cell of the first column of memory cells or the second column of memory cells is a non-volatile memory cell.
 9. The memory cell array of claim 8, wherein the non-volatile memory cell includes one or more of a resistance random access memory (RRAM), a ferroelectric RAM (FRAM) or a Magnetoresistive RAM (MRAM).
 10. The memory cell array of claim 7, wherein a resistance of the first bit line or a resistance of the second bit line is substantially equal to a resistance of the source line.
 11. The memory cell array of claim 7, wherein the source line comprises: a third conductive line extending in the second direction, and being located on a third metal layer below the first metal layer.
 12. The memory cell array of claim 11, wherein the source line further comprises: a fourth conductive line extending in the second direction, and being located on a fourth metal layer above the third metal layer and below the first metal layer; and a second set of vias electrically coupled to the third conductive line and the fourth conductive line, and being located between the third conductive line and the fourth conductive line.
 13. The memory cell array of claim 12, wherein the third metal layer is a metal 1 (M1) layer, and the fourth metal layer is a metal 2 (M2) layer.
 14. The memory cell array of claim 7, wherein the first metal layer is a metal 4 (M4) layer, and the second metal layer is a metal 5 (M5) layer.
 15. The memory cell array of claim 7, wherein a length of the first conductive line is substantially equal to a length of the second conductive line.
 16. A method of forming a memory cell array, the method comprising: generating, by a processor, a layout design of the memory cell array, wherein the generating of the layout design comprises: placing a first set of memory cell layout patterns in a first column, the first set of memory cell layout patterns corresponding to fabricating a first set of memory cells, each layout pattern of the first set of memory cell layout patterns being separated from an adjacent layout pattern of the first set of memory cell layout patterns in a first direction; placing a second set of memory cell layout patterns in a second column separated from the first column in a second direction different from the first direction, the second set of memory cell layout patterns corresponding to fabricating a second set of memory cells, each layout pattern of the second set of memory cell layout patterns being separated from an adjacent layout pattern of the second set of memory cell layout patterns in the first direction; placing a first set of conductive feature layout patterns in the first column, the first set of conductive feature layout patterns extending in the first direction and overlapping the first set of memory cell layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a first bit line extending in the first direction and being coupled to the first set of memory cells; and placing a second set of conductive feature layout patterns in the second column, the second set of conductive feature layout patterns extending in the first direction and overlapping the second set of memory cell layout patterns, the second set of conductive feature layout patterns corresponding to fabricating a second bit line extending in the first direction and being coupled to the second set of memory cells; and manufacturing the memory cell array based on the layout design.
 17. The method of claim 16, wherein the placing the first set of conductive feature layout patterns comprises: placing a first conductive feature layout pattern on a first layout level, the first conductive feature layout pattern extending in the first direction, and the first conductive feature layout pattern corresponding to fabricating a first portion of the first bit line coupled to the first set of memory cells; and placing a second conductive feature layout pattern on a second layout level different from the first layout level, the second conductive feature layout pattern extending in the first direction, and the second conductive feature layout pattern corresponding to fabricating a second portion of the first bit line coupled to the first set of memory cells; and the generating the layout design of the memory cell array further comprises: placing a first set of via layout patterns between the first layout level and the second layout level, and the first set of via layout patterns corresponding to fabricating vias coupled between the first portion of the first bit line and the second portion of the first bit line.
 18. The method of claim 16, wherein the generating the layout design of the memory cell array further comprises: placing a third set of conductive feature layout patterns between the first set of memory cell layout patterns and the second set of memory cell layout patterns, the third set of conductive feature layout patterns extending in the first direction, the third set of conductive feature layout patterns corresponding to fabricating a source line extending in the first direction and being coupled to the first set of memory cells and the second set of memory cells.
 19. The method of claim 18, wherein the placing the third set of conductive feature layout patterns between the first set of memory cell layout patterns and the second set of memory cell layout patterns comprises: placing a first conductive feature layout pattern on a first layout level, the first conductive feature layout pattern extending in the first direction, and the first conductive feature layout pattern corresponding to fabricating a first portion of the source line coupled to the first set of memory cells and the second set of memory cells; and placing a second conductive feature layout pattern on a second layout level different from the first layout level, the second conductive feature layout pattern extending in the first direction, and the second conductive feature layout pattern corresponding to fabricating a second portion of the source line coupled to the first set of memory cells and the second set of memory cells; and the generating the layout design of the memory cell array further comprises: placing a first set of via layout patterns between the first layout level and the second layout level, and the first set of via layout patterns corresponding to fabricating vias coupled between the first portion of the source line and the second portion of the source line.
 20. The method of claim 16, wherein the placing the first set of memory cell layout patterns or the second set of memory cell layout patterns comprises: placing a first selector element layout pattern in the first column or the second column, the first selector element layout pattern corresponding to fabricating a first selector element, the first selector element layout pattern being located on a first set of layout levels; placing a first electrode element layout pattern on a first layout level, the first electrode element layout pattern corresponding to fabricating a bottom electrode element of a resistive switching element, the resistive switching element being coupled to the first selector element; placing a second electrode element layout pattern on a second layout level different from the first layout level, the second electrode element layout pattern corresponding to fabricating a top electrode element of the resistive switching element; and placing a resistive switching material layout pattern between the first layout level and the second layout level, the resistive switching material layout pattern corresponding to fabricating a resistive switching material of the resistive switching element. 